New Intel Stratix 10 FPGA Drivers Coming To Linux 4.21 Kernel

Written by Michael Larabel in Intel on 27 November 2018 at 08:30 PM EST. Add A Comment
At the end of last year Intel announced the Stratix 10 FPGA with HBM2 memory for HPC workloads. With the Linux 4.21 kernel cycle, the support for this hardware will be further improved upon for FPGA programming with the mainline kernel.

The 14nm FinFET Stratix 10 with its 512GB/s of High Bandwidth Memory 2 is intended for high-performance computing, data centers, network virtualization, and similar use-cases. The Stratix FPGAs were originally developed by Altera, which Intel acquired a few years back. Those unfamiliar with Stratix 10 can learn more at Intel does offer a Stratix 10 Developer Kit but is priced at around $8,000 USD.

With the Linux 4.21 kernel that will officially kick off its merge window at around the start of 2019, more Stratix code will be squared away for the mainline kernel. Some of that code was merged today into char-misc-next as the step ahead of being mainlined into the kernel.

The first new Stratix 10 driver is a Service Layer Driver, which is used for granting higher level privileges to the SoC. The patch introducing the new driver explained, "Some features of the Intel Stratix10 SoC require a level of privilege higher than the kernel is granted. Such secure features include FPGA programming. In terms of the ARMv8 architecture, the kernel runs at Exception Level 1 (EL1), access to the features requires Exception Level 3 (EL3). The Intel Stratix10 SoC service layer provides an in kernel API for drivers to request access to the secure features. The requests are queued and processed one by one. ARM’s SMCCC is used to pass the execution of the requests on to a secure monitor (EL3)."

With the Stratix 10 Service Layer Driver in place, the second driver added is the SoC FPGA Manager Driver. This manager driver is used for reconfiguring the Stratix 10 SoC FPGA devices using the service layer driver to communicate with the privileged hardware to achieve the FPGA programming.
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