Intel Cascade Lake Support Posted For The GCC Compiler

Written by Michael Larabel in Intel on 21 November 2018 at 06:10 AM EST. 2 Comments
Intel developers have submitted their GCC compiler enablement patch for the Cascade Lake 14nm CPUs due out starting in early 2019.

The GNU Compiler Collection patch adds support for the -march=cascadelake target for generating optimized code for these upcoming server and enthusiast class processors.

The "cascadelake" target for GCC enables MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI. We have already known Cascade Lake would have support for new deep learning instructions so it is not surprising to see the AVX-512 VNNI support.

It was October of last year that Intel originally added the VNNI code to GCC for "Virtual Neural Network Instruction" with originally being intended for their Icelake CPU target, which has been in GCC already.

Cascade Lake is still using the Intel Skylake cost table. There are no other surprises or new information revealed about Cascade Lake as part of the compiler patch.

This "cascadelake" target should be included for the GCC 9 compiler release due out in early 2019.
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