AMD To Optimize C3 Entry On Linux By Finally Skipping The Cache Flush
The optimization posted is around the ACPI C3 power state handling on Linux for AMD processors. Right now when a CPU core enters the C3 power sleep state, its cache is flushed even though the cache may be shared with CPU cores that are not in the sleep state. As the AMD patch notes, "this will cause performance drop for the cores which share some caches."
Thus the new patch to optimize the C3 entry on AMD CPUs is now having that cache flushing skipped as it's not necessary for their processors and can avoid potentially hurting the performance for other cores with shared cache.
That flushing on C3 sleep is the default behavior with the kernel for cache coherence purposes. Up to now within the Linux kernel Intel CPUs unconditionally already avoided that cache flush on C3 entry. All Zhaoxin CPUs had this basic optimization too on Linux as well as newer Centaur CPUs (depending upon microcode version) were skipping their cache flushing on C3 entry, but now AMD has joined the party too.