Machine Check Banks To Double With Future AMD CPUs
In preparation for "future AMD systems", which is likely AMD EPYC Zen 3 "Milan" server processors, there will be more banks for the Machine Check Exception handling.
Banks for the Machine Check Architecture are a means of organizing subsystems/subevents with their relevant MSRs for detecting/reporting machine errors. Older processor families had only a few banks of registers for machine check support while the current limit in the AMD MCE driver has been 32 banks. With a patch queued in ras/core ahead of Linux 5.10, that maximum number of banks is being increased from 32 to 64.
The patch by one of AMD's engineers simply notes, "Increase maximum number of banks to 64 because future AMD systems will support up to 64 MCA banks per CPU."
It will be interesting to see what's in store with the machine check improvements for future AMD CPUs, which given the timing will likely be with Zen 3 server CPUs.
Banks for the Machine Check Architecture are a means of organizing subsystems/subevents with their relevant MSRs for detecting/reporting machine errors. Older processor families had only a few banks of registers for machine check support while the current limit in the AMD MCE driver has been 32 banks. With a patch queued in ras/core ahead of Linux 5.10, that maximum number of banks is being increased from 32 to 64.
The patch by one of AMD's engineers simply notes, "Increase maximum number of banks to 64 because future AMD systems will support up to 64 MCA banks per CPU."
It will be interesting to see what's in store with the machine check improvements for future AMD CPUs, which given the timing will likely be with Zen 3 server CPUs.
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