Coreboot Lands More RISC-V / lowRISC Code
Written by Michael Larabel in Coreboot on 25 October 2016 at 08:50 PM EDT. 7 Comments
As some early post-Coreboot 4.5 changes are some work to benefit fans of the RISC-V ISA.

Hitting Coreboot Git with this commit by Ron Minnich is a clean-up of the RISC-V code. He mentioned with the changes, "This version of coreboot successfully starts a Harvey (Plan 9) kernel as a payload, entering main() with no supporting assembly code for startup. The Harvey port is not complete so it just panics but ... it gets started. We provide a standard payload function that takes a pointer argument and makes the jump from machine to supervisor mode; the days of kernels running in machine mode are over."

Then today Minnich added initial lowRISC SoC support. For the uninformed, lowRISC is one an open-source, Linux-capable RISC-V based SoC design that's still in-progress but quickly becoming a reality.
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Michael Larabel is the principal author of and founded the site in 2004 with a focus on enriching the Linux hardware experience. Michael has written more than 10,000 articles covering the state of Linux hardware support, Linux performance, graphics drivers, and other topics. Michael is also the lead developer of the Phoronix Test Suite, Phoromatic, and automated benchmarking software. He can be followed via Twitter or contacted via

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