DDR5 Memory Channel Scaling Performance With AMD EPYC 9004 Series

Written by Michael Larabel in Memory on 6 January 2023 at 07:30 AM EST. Page 2 of 6. 15 Comments.

With NASA's NAS Parallel Benchmarks for its Integer Sort (IS) benchmark driven by random memory access performance, to no real surprise it was scaling well up through the 12 memory channel configuration of Genoa.

Similarly, with NPB's multi-grid (MG)) test on a sequence of meshes was showing strong and consistent performance uplift through the 12 memory channel support of Genoa.

NPB's Scalar Penta-diagonal solver further reinforced the effectiveness of 12 channels of DDR5 server memory support with 4th Gen EPYC.

The nekRS Navier Stokes solver was showing great scaling up through the 12 memory channels.

The open-source OpenFOAM computational fluid dynamics (CFD) package does a great job of showing the benefits of up to twelve DDR5-4800 memory channels in the real-world and the impact on performance. Here though the benefit of going from 10 to 12 memory channels was much less significant for a medium-sized model, if looking to shave off some CFD server costs.

Related Articles