RISC-V Vector ISA Support Slated For Linux 6.5

Written by Michael Larabel in RISC-V on 12 June 2023 at 06:29 AM EDT. 8 Comments
Support for RISC-V's Vector ISA is now expected to be merged for the upcoming Linux 6.5 kernel merge window.

This new code provides the necessary Linux kernel changes for dealing with RISC-V's "V" Vector Extension, including new prctl() interfaces so user-space can check on the status of Vector extension support. a new sysctl knob "riscv_v_default_allow" to adjust changing the default for allowing Vector extension use by user-space software, the "RISCV_ISA_V" Kconfig option for toggling kernel build support with this ISA extension, and various other changes.

The RISC-V Vector Extension 1.0 was ratified in 2021 and intended to allow versatile SIMD on the royalty-free CPU architecture. This RISC-V Vector support is intended to help with the architecture's applications in the data center and elsewhere. The RISC-V Vector extension aims for high performance and efficient vector processing, support for domain-specific features in areas like machine learning and graphics depending upon the ISA/CPU implementation, and support for SIMD-type operations and other features.

SiFive has been working on this RISC-V Vector support for the Linux kernel going back to last year for this modern implementation. While the V extension was in draft form, there was even other kernel patches proposed going back to 2020. Concurrently there has been the RISC-V Vector preparations also going into the relevant open-source compiler toolchain components.

RISC-V Vector

The milestone now achieved is that the RISC-V Vector ISA support for the Linux kernel has been merged by maintainer Palmer Dabbelt into the riscv/linux.git's for-next branch. With it making the for-next branch, it should in turn be submitted to mainline with the upcoming Linux 6.5 kernel merge window as part of the RISC-V port updates for this next kernel cycle.
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