RISC-V Lands New Extensions In Linux 6.0

Written by Michael Larabel in RISC-V on 13 August 2022 at 05:32 AM EDT. 3 Comments
Last week was the main set of RISC-V updates for Linux 6.0 that included improving Svpbmt support, a more robust default kernel configuration, and other improvements. A secondary set of RISC-V CPU architecture updates has now been merged for Linux 6.0.

This second set of RISC-V updates for the Linux 6.0 merge window include new extensions and other work.

Zicbom support has been merged. Zicbom is RISC-V's cache block management operations extension and part of their broader Cache Management Operations (CMOs) work for the architecture. The kernel integration allows using Zicbom for handling cache flushing and other cache management related operations. The Linux kernel also adapted to deal with the non-standard cache management operations on the Allwinner D1 SoC.

Zihintpause was also merged for use as a go-slow instruction in cpu_relax(). Zihintpause was ratified last year as a way for providing "pause hints" and is intended to help reduce the energy consumption of RISC-V hardware and improve the performance of spin-wait loops and more.

Sstc is another new RISC-V extension now supported for supervisor-mode timer/counter management.

This second set of RISC-V updates for Linux 6.0 also includes DeviceTree clean-ups, various fixes and clean-ups to the RISC-V PMU driver, and other changes.

This latest set of RISC-V changes for the Linux kernel, which were already merged, can be found via this pull request.
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