LLVM Lands New Backend For Xtensa Architecture

Written by Michael Larabel in LLVM on 3 January 2023 at 05:53 AM EST. 7 Comments
The newest CPU back-end added to the LLVM compiler stack is for Xtensa processor cores.

Cadence's Xtensa instruction set can now be targeted by the LLVM/Clang compiler after the initial set of 10 patches were merged this past week. Xtensa can be used for DSPs and micro-controllers up through neural network processors and data processing engines. For those that haven't looked into Xtensa recently, Cadence promotes it as:
"Cadence® Tensilica® Xtensa® processors combine the best of CPUs, GPUs, FPGAs, and dedicated custom RTL in ASICs/SoCs and enable the development of energy-efficient domain-specific processors that offer high performance, flexibility for future-proofing, and more importantly, can be tailored for your specific application requirements. Xtensa processors are based on a modular, highly flexible 32-bit RISC architecture that can easily scale from a tiny, cache-less controller or task engine to a high-performance SIMD/VLIW DSP. Furthermore, to facilitate the development of SoCs for functional safety, the Xtensa architecture supports a windowed watchdog timer (WWDT) and FlexLock including dual-core lockstep (DCLS)."

Cadence has offered their "XT-CLANG" toolchain that is a downstream of the LLVM/Clang C/C++ compiler with Xtensa support as well as offering the Xplorer IDE with GUI. Now though with LLVM 16 due out around March will be the initial upstream Xtensa support.

Stefan Stipanovic and Andrei Safronov of Espressif Systems are the ones that have been working on the upstream LLVM Xtensa support. See these commits if interested in the upstream, open-source Xtensa compiler support.
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