LLVM 17 Lands Initial Support For RISC-V Vector Crypto Extension ISA

Written by Michael Larabel in LLVM on 26 March 2023 at 06:54 AM EDT. 1 Comment
Merged this weekend to the LLVM 17 development code-base is initial support for RISC-V's vector crypto extension ISA.

The latest LLVM (17) Git code has initial support for the v0.3 draft specification of the vector crypto extension ISA, which aims to speed-up cryptographic operations on future RISC-V processors. These instructions were developed by Brandon Wu at SiFive.

For those interested the tentative RISC-V cryptography extensions are outlined in the RISC-V crypto GitHub repository.

Microsemi RISC-V crypto presentation

Microsemi a while back also provided a presentation on RISC-V crypto extensions here.

This commit has the experimental instructions for ZVKB, ZVKG, ZVKN, ZVKNHA, ZVKNHB, ZVKNS, ZVKS, ZVKSED, and ZVKSH. LLVM 17.0 with this vector crypto work and other RISC-V improvements -- and a whole lot more compiler work at large -- should be out in the usual September timeframe.
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