LLVM 16.0.1 Released With Many Compiler Fixes, Backports AMD Zen 4 Scheduler Model

It's been two weeks already since the release of LLVM 16.0 as the latest shiny feature update to this widely-used, open-source compiler stack. LLVM release manager Tom Stellard today issued LLVM 16.0.1 as the first point release with a wide collection of fixes and other maintenance work to LLVM and its contained sub-projects.

LLVM 16.0 introduced more C and C++ language features, faster LLVM LLD linking, Zstd compressed debug sections, the LoongArch CPU back-end was promoted out of being experimental, various new Intel instruction set extensions added, initial AMD Zen 4 (znver4) support, new Arm and RISC-V features, and much more that was built up over the past half-year.

LLVM 16.0.1 takes care of some early fallout from that big release and marks the first of numerous bi-weekly point releases to come. With LLVM 16.0.1 there is now support for emulated TLS on RISC-V, support for load/store for BF16 in AVX, and other random fixes throughout.

Arguably most exciting with LLVM 16.0.1 is that it has back-ported the new AMD Zen 4 scheduler model for the znver4 targeting. With LLVM 16 since the Znver4 target was introduced, it began as Znver3 and then simply enabled the new instruction set extensions found with Zen 4 like AVX-512. But the scheduler model stayed the same as Zen 3 even though instruction costs differed with this latest-generation EPYC and Ryzen processors. But then in early March, AMD provided the tuned Zen 4 model for LLVM that was merged for LLVM 17. That Zen 4 model (tested/tuned on EPYC 9004 "Genoa" CPUs) has been backported and found now with LLVM 16.0.1 stable. It will be interesting now to fire up some new LLVM / GCC / AOCC compiler benchmarks on AMD Ryzen 7000 series and EPYC 9004 series processors.

The full list of LLVM 16.0.1 changes can be found via the LLVM Discourse. LLVM 16.0.1 downloads are available from GitHub.