Ingenic X2000/X2000E MIPS IoT Processor Supported By Linux 5.10
The Linux 5.10 kernel is bringing support for new MIPS-based Ingenic SoCs.
The China-based Ingenic Semiconductor announced the X2000 series this summer as the latest in their XBurst2-based SoCs that are based on the MIPS32 architecture. The X2000/X2000E is designed for use within IoT applications as alternatives to ARM and RISC-V SoCs.
The Ingenic X2000/X2000E are fabbed at 28nm and feature two MIPS32 cores clocked at 1.2~1.5GHz. The X2000 supports 128MB of LPDDR3 memory while the X2000E can handle 256MB of LPDDR2 memory. Again, these SoCs are intended just for specialized IoT use-cases.
With the Linux 5.10 kernel there is now the bits added for detecting the Ingenic X2000 series. Additionally, there is a DeviceTree addition for supporting the YSH/ATIL CU2000 module with Neo backplane development board that uses the Ingenic X2000E.
The MIPS changes this cycle also now allow Ingeic SoC support to be built into generic MIPS kernel images and have other general MIPS improvements too.
The China-based Ingenic Semiconductor announced the X2000 series this summer as the latest in their XBurst2-based SoCs that are based on the MIPS32 architecture. The X2000/X2000E is designed for use within IoT applications as alternatives to ARM and RISC-V SoCs.
The Ingenic X2000/X2000E are fabbed at 28nm and feature two MIPS32 cores clocked at 1.2~1.5GHz. The X2000 supports 128MB of LPDDR3 memory while the X2000E can handle 256MB of LPDDR2 memory. Again, these SoCs are intended just for specialized IoT use-cases.
With the Linux 5.10 kernel there is now the bits added for detecting the Ingenic X2000 series. Additionally, there is a DeviceTree addition for supporting the YSH/ATIL CU2000 module with Neo backplane development board that uses the Ingenic X2000E.
The MIPS changes this cycle also now allow Ingeic SoC support to be built into generic MIPS kernel images and have other general MIPS improvements too.
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