Last Minute Sapphire Rapids Change Lands In GCC 12

Written by Michael Larabel in Intel on 18 March 2022 at 05:26 AM EDT. Add A Comment
A small but important change was just merged into GCC 12 ahead of its upcoming release in a month or so and also the same patch back-ported now for the GCC 11 stable series.

It was just recently noticed the -march=sapphirerapids tuning for the GNU Compiler Collection was using Intel Cooper Lake as its base and tacking the various extra instruction set extensions on top. However, it should have been Ice Lake Server as the base target for building upon to meet the Sapphire Rapids ISA capabilities.

This patch was merged into GCC 12 this morning for straightening things up so Sapphire Rapids is based on Ice Lake Server, not the niche Cooper Lake.

Within the GCC documentation it also updates the Intel Xeon Sapphire Rapids capabilities for the "-march=sapphirerapids" targeting with the CPU supporting x86_64 with MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2, VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16, and AVX512BF16 instruction set support.

This same patch should also work its way into the GCC 11.3 stable compiler update too.
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