Updated AMD Zen Scheduler Model Lands For LLVM 6.0
Written by Michael Larabel in AMD on 31 August 2017 at 10:32 AM EDT. 15 Comments
AMD --
With the soon-to-be-released LLVM 5.0 there is the initial AMD Zen scheduler model for the compiler to benefit Ryzen / EPYC processors. But now already hitting the LLVM development code for LLVM 6.0 is a revised scheduler model.

AMD's Ganesh Gopalasubramanian posted an updated scheduler model for "znver1", the first-generation AMD Zen processors. Today it's now been merged in the development code to be released as part of LLVM 6.0 in another six months. Changes mentioned include:
1) Regex based Instruction itineraries for integer instructions.
2) The instructions are grouped as per the nature of the instructions (move, arithmetic, logic, Misc, Control Transfer).
3) FP instructions and their itineraries are added which includes values for SSE4A, BMI, BMI2 and SHA instructions.

It looks like I'll be working on some updated Ryzen/Threadripper LLVM Clang 4/5/SVN benchmarks this weekend and possibly some fresh GCC numbers as well.
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