Intel Updates Alder Lake Tuning For GCC, Reaffirms No Official AVX-512
With GCC 11 stable and GCC 12 up to now, making use of -march=alderlake or -mtune=alderlake has been carrying the existing Ice Lake cost table tuned for their prior-generation cores. But now with Alder Lake all firmed up and shipping, a proper Alder Lake cost table is set to be added to the GCC compiler for more accurate instruction and register allocation costs relevant to these latest generation processors. It will be interesting to see how much of an improvement this new cost table has and how well it behaves considering the new hybrid architecture with the mix of Golden Cove and Gracemont cores whether it's more tuned for those P cores or not.
The tuning also flips on Alder Lake for a few x86 tuning optimizations too while removing Alder Lake from a few x86 tuning optimizations focused on AVX-256/AVX-512 and previously flipped on for Alder Lake with last year's enablement patch.
While Intel is not officially supporting AVX-512 on Alder Lake, AVX-512 works if disabling all of the E cores and turning on AVX-512 for the firmware. Intel though isn't officially supporting that and with today's Alder Lake tuning patch they reaffirm no AVX-512 support. "Update mtune for alderlake, Alder Lake Intel Hybrid Technology will not support Intel AVX-512. ISA features such as Intel AVX, AVX-VNNI, Intel AVX2, and UMONITOR/UMWAIT/TPAUSE are supported."
This patch posted today provides that new cost table and other tuning for Alder Lake. Permission is being sought to land it into GCC 12's development branch. Once that happens I'll be around with some fresh Alder Lake benchmarks while the GCC 12.1 stable release isn't expected until the ~April timeframe.