Originally posted by vladpetric
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Intel Rolls Out 10nm Pentium/Celeron CPUs, Previews Rocket Lake
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Originally posted by hajj_3 View PostThose celeron and pentium chips don't use Xe graphics
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Originally posted by M@GOid View PostThey don't have AVX? Ouch. Didn't some big distro drew the line of support on AVX capable CPUs recently? If that is the case, those brand new CPUs wouldn't be supported.
See: https://www.phoronix.com/scan.php?pa...86-64-v2-Plans
* Thanks to Space Heater for the correction.Last edited by coder; 11 January 2021, 10:30 PM. Reason: Previously cited Fedora. Fixed to say RHEL 9 (see reference).
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Originally posted by M@GOid View PostTo be fair, AMD's side isn't much prettier. ECC support was left to motherboard manufacturers and most don't do it. I heard that only Ryzen-pro models really support ECC on enterprise-class PCs.
When it comes to ECC support, Pro/non-Pro makes a difference only for APUs.
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Originally posted by M@GOid View PostTo be fair, AMD's side isn't much prettier. ECC support was left to motherboard manufacturers and most don't do it. I heard that only Ryzen-pro models really support ECC on enterprise-class PCs.
The ECC situation at the low end isn't pretty. You basically have to get a special SKU specified for industrial or embedded use. As I mentioned above, Intel sells their small-core based Industrial CPUs under the Atom brand. AMD sells embedded-oriented APUs with ECC support, as well, but they're BGA (i.e. not socketed). AFAIK, none of Intel's small-core CPUs are socketed, either.
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Originally posted by chithanh View PostHowever nowadays (since X570/B550) all big mobo vendors except MSI support ECC on AM4.
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Originally posted by coder View PostNo, but they actually sell Atom-branded CPUs which pair up to 16 small cores with ECC memory support and more PCIe lanes. Of course, they're in a different price range, but it's not like there is no option provided whatsoever.
https://ark.intel.com/content/www/us...anelLabel29035
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Originally posted by vladpetric View PostOTOH AVX isn't exactly a power-friendly instruction set ... if you want 6W TDP, you gotta sacrifice some stuff.
In terms of area, AVX bloats the register file, but I wonder if that's even enough to bother about.
Anyway, let's not forget this is a 10-way core with 6-wide decode! So, we're not exactly talking about a microcontroller or IoT core. And its ancestors had SSE/SSE2 going at least as far back as the 22 nm days, so you'd expect at least basic AVX/AVX2-support wouldn't be completely off the table.
In case you missed it: https://en.wikichip.org/wiki/intel/m...t#Architecture
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Originally posted by vladpetric View PostYeap, unfortunately they are indeed small cores - the single threaded performance of those is pretty poor compared to even a Pentium.
Considering its power envelope, that's substantial.
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Originally posted by vladpetric View PostYou know, there is actually a way to test it out to some degree. With an AMD Ryzen retail, on an x570 pro mobo or similar, you try vanilla rowhammer (not ECCploit) ... If you're successful at vanilla rowhammer, it means that ECC doesn't work. If you're not successful ... well, you haven't really learnt much.
Another option is to try an ECC DIMM that's known to be defective.
Probably the best (and most difficult) is to use the kernel-support for injecting faults, and see if they're reported. A guy in the RealWolrdTech thread where Linus posted was talking about this, but hadn't updated with his relults, last I checked.
BTW, someone posted a link to an article showing that rowhammer is still possible (though much more difficult), even with ECC. But, what should be a lot easier is to try rowhammer and see if it causes an ECC event. That's all you need -- for it to trigger a correctable error. However, if your ECC support is indeed broken, then I guess you'd get a successful rowhammer, instead.
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