Intel Rolls Out 10nm Pentium/Celeron CPUs, Previews Rocket Lake

[coder]

TBH they kind of skipped the 5th gen by not really releasing more than token Broadwell dektop offerings.

It was still a design iteration and had its own 5000-series numbering. And as a partial substitute, they released the Haswell-Refresh series (although that was still numbered as part of the 4000-series).

[coder]

What happened to the fused Intel+AMD GPU laptop chip?

Long-ago discontinued. What did you expect?

• https://www.anandtech.com/show/14957...keg-processors
• https://www.anandtech.com/show/15836...river-in-limbo

[coder]

Nobody has yet mentioned the 14nm Rocket Lake desktop CPUs. Anandtech noticed a mention of 125 W TDP (with 250 W turbo), in the footnotes of one of their slides. I wonder where that'll put its base clocks.

[Space Heater]

Not exactly. Fedora is drawing the line at "near-Nehalem", which is the ISA level before AVX and a bar which these definitely clear.

RHEL 9 is doing this, but when did Fedora decide to switch to that?

[Templar82]

https://en.wikipedia.org/wiki/Scienc...nd_mathematics

I know what STEM stands for... I want to know what exactly is 78% faster.

[coder]

RHEL 9 is doing this, but when did Fedora decide to switch to that?

You're right -- my bad. I'll fix my original post.

Here's the article: https://www.phoronix.com/scan.php?pa...86-64-v2-Plans

[vladpetric]

They could still split them in half and execute them as 2x 128-bit parts. Didn't AMD do that in Zen1? I know Pentium did that with SSE, in the Pentium 4.

In terms of area, AVX bloats the register file, but I wonder if that's even enough to bother about.

Anyway, let's not forget this is a 10-way core with 6-wide decode! So, we're not exactly talking about a microcontroller or IoT core. And its ancestors had SSE/SSE2 going at least as far back as the 22 nm days, so you'd expect at least basic AVX/AVX2-support wouldn't be completely off the table.

In case you missed it: https://en.wikichip.org/wiki/intel/m...t#Architecture

Register file, ALUs, and bypass networks cost significantly more power when things are 256-wide.

Sure, they could split them into 2x 128 bits, but then you could also just be using regular SSE42 (AMD has a few instructions that work on their early processors, but performance sucks to the point that it's not worth using the specialization; my main beef is with pext/pdep)

Look, you're generally making good points, I don't mean to nitpick.

[coder]

Look, you're generally making good points, I don't mean to nitpick.

Thanks. No worries.

[vladpetric]

They could still split them in half and execute them as 2x 128-bit parts. Didn't AMD do that in Zen1? I know Pentium did that with SSE, in the Pentium 4.

In terms of area, AVX bloats the register file, but I wonder if that's even enough to bother about.

Anyway, let's not forget this is a 10-way core with 6-wide decode! So, we're not exactly talking about a microcontroller or IoT core. And its ancestors had SSE/SSE2 going at least as far back as the 22 nm days, so you'd expect at least basic AVX/AVX2-support wouldn't be completely off the table.

In case you missed it: https://en.wikichip.org/wiki/intel/m...t#Architecture

I'm curious what out-of-order decode actually means. Do you know?

I kinda' doubt that they're doing out-of-order fetch.

Decoding instructions is for the most part stateless (first instruction doesn't affect the decoding of the second instruction, unless you do some fusion at decode), so it doesn't matter too much the order in which you decode them, as long as you rename them in the correct order.

[vladpetric]

They could still split them in half and execute them as 2x 128-bit parts. Didn't AMD do that in Zen1? I know Pentium did that with SSE, in the Pentium 4.

In terms of area, AVX bloats the register file, but I wonder if that's even enough to bother about.

Anyway, let's not forget this is a 10-way core with 6-wide decode! So, we're not exactly talking about a microcontroller or IoT core. And its ancestors had SSE/SSE2 going at least as far back as the 22 nm days, so you'd expect at least basic AVX/AVX2-support wouldn't be completely off the table.

In case you missed it: https://en.wikichip.org/wiki/intel/m...t#Architecture

Yeah it looks like a great Atom, not yet available but hopefully it should be arriving soon.