SiFive To Release Code As Open-Source For Fully Initializing The RISC-V Board

Last week we noted how some of the code to boot the RISC-V SiFive HiFive Unleashed development board was closed-source. That upset some in the Coreboot community with hoping for a more open development board built around the RISC-V open-source processor ISA. The good news is that SiFive will soon be releasing the necessary code for initialization as open-source.

The code for initializing the DDR controller was not open-source and SiFive believed they could not open-source it. The good news is that SiFive has discovered they will be able to open-source it.

SiFive's Wesley Terpstra has shared, "SiFive is committed to supporting the open-source community. We are pleased to report that after discussions with our IP partners, we are now able to make available all the source code required to initialize the HiFive Unleashed board. The board’s boot sequence is described in the manual. The assembly code in the initial reset ROM is listed in the manual Chapter 6.1 “Reset Vector”. The firmware in the ZSBL mask ROM is directly readable by software on the chip, and we will be making the full source code available shortly. The source code for FSBL including the DDR initialization will also be available shortly. We can attest there is no other firmware run by the system during boot."

That's quite good news for this main RISC-V development board to date. The HiFive Unleashed with U540 SoC offers a 4+1 multi-core 1.5GHz CPU design, Linux-capable, Gigabit Ethernet, 8GB of DDR4 memory, microSD card, and retails for $999 USD.