It Turns Out RISC-V Hardware So Far Isn't Entirely Open-Source

While free software/hardware advocates have been ecstatic about the RISC-V open-source, royalty-free processor architecture, hardware so far hasn't been as open as desired.

While this processor ISA is entirely open and living up to its merits, it turns out the RISC-V implementations so far haven't been quite as open as one would have thought. A Phoronix reader pointed out to us some remarks by developers on the main RISC-V development board out so far, the SiFive HiFive Unleashed

Ron Minnich who has run the Coreboot project for more than the past decade and spearheads the effort of getting Coreboot on new Chrome OS devices at Google, commented on the Unleashed development board this weekend:

All this said, note that the HiFive is no more open, today, than your average ARM SOC; and it is much less open than, e.g., Power. I realize there was a lot of hope in the early days that RISC-V implied "openness" but as we can see that is not so. There's blobs in HiFive.

Open instruction sets do not necessarily result in open implementations. An open implementation of RISC-V will require a commitment on the part of a company to opening it up at all levels, not just the instruction set.

While they are trying to make it an open board, as it stands now Minnich just compares this RISC-V board as being no more open than an average ARM SoC and not as open as IBM POWER.

Ron further commented that he is hoping for other RISC-V implementations from different vendors be more open.

Jonathan Neuschäfer also commented on that thread was a SiFive comment that they are not able to provide the initialization sequence for the DRAM controller. SiFive suggests reverse-engineering / disassembling the binaries for this data.