DDR4 vs. DDR5 Memory Performance For Intel Core i5-12600K Alder Lake On Linux

[Michael]

You really should update your benchmark suite to use a new build of 7-zip. v16.02 is 4.5yrs old. Lots of optimisations have been made since then.

What's being benchmarked is the hardware and not the 7-zip application, and using the same version for 4.5 years means that we can get stable numbers for the differences between various cpu:s for that time period.

The issue is that the public sources for 7-Zip still don't have proper build system support for Linux... They are putting out Linux binaries now, but their public sources still have a Makefile that is incomplete/broken even with the latest version, unless there is some other undocumented way for compiling on Linux.

[F.Ultra]

The issue is that the public sources for 7-Zip still don't have proper build system support for Linux... They are putting out Linux binaries now, but their public sources still have a Makefile that is incomplete/broken even with the latest version, unless there is some other undocumented way for compiling on Linux.

So it's incidentally giving us a good baseline then

[torsionbar28]

My first DDR4 setup was clocked at 3200 (some kind of overclock gamer sticks, not some IBM/Dell branded shit sticks). I didn't even buy the most performant system, actually. I think my current, 2nd gen machine with DDR4 has DDR4-4200 or 4400 modules.

edit: yea, re-checked. The fastest ddr4 on the market in 5333.

As I mentioned, my numbers are the JEDEC standards. Anything above that is not. Of course there are XMP profiles and manual overclocking for those who are into that sort of thing, but those are a niche within a niche, not really worth mentioning in a broader discussion about memory technology standards.

[AlB80]

Ok. Obviously both have 16Gbit x8 chips, so it's best case for DDR5 (32GB module) and worst for DDR4 (16GB). Why?
DDR4 memory controller have only 32 banks in total (2 ch x 1 rank x 16 banks per rank).
DDR5 memory controller have 128 banks in total (2 ch x 2 subch x 2 rank x 32 banks per rank).
DDR4 memory transactions are often stalled due to bank collisions, thus even DDR4 good timings are not enough.

Erratum. DDR5 memory controller have 256 banks in total.
F.e. the probability that a bank collision will occur for 10 simultaneous transactions = 1 - bank! / (bank - tx)! / bank^tx
DDR4 = 79.2%
DDR5 = 16.3%
For DDR4, this means that a single ranked module sucks under multithreaded load, and a latency estimate can be doubled or tripled.
Of course, all hi-freq modules are single ranked.

[coder]

Michael, for some reason this article isn't loading past about the first page worth of content. I can view the graphs in other articles I checked, so I think it's probably not an IP-block, like last time.