AMD Announces Zen 4C Cores Coming To Ryzen Laptops

[Anux]

it is not in there for the amd side but for intel... they say to get the 6ghz goal intel is forced to make the transistors bigger.

Am I blind? I can't find that either?

the quote is form a commend:

And we can't be sure if that is the truth or just someone that doesn't know better.

High-speed design uses extra transistors and elements (or larger transistors) and many locations to improve the achieved clock frequencies. Zen 4c eliminates this, as it only expects or aims to run at significantly lower clock speeds. The resulting circuit can then be implemented in a smaller footprint. Different parts of the core are said to have their area reduced by up to 35–45%. This is while using the same 5nm node (TSMC N5). The key to this increase is believed to be mainly the simplification of the wiring (in the metal layers) between the transistors that results from the abandonment of high-speed design."

This doesn't seem to confident either. Speculation about more transistors, which is definitely wrong and speculation about smaller transistors which might be true. But then it contradicts itself with "The key to this increase is believed to be mainly the simplification of the wiring".

The articles I read so far that are based on AMDs publications all cited the reduction of unused areas. And for me that is the most logical version because if we look at L2 cache (which has no unused areas to begin with) there is no reduction in size that should be there if transistors were smaller (remember one bit cache consists of 8 transistors).

The article says: "a lower operating clock enables designers to squeeze signal paths closer together and improve standard cell density."

Don't confuse density with transistor size. If I can squeeze more people in a room the density increases, everyone is closer together but the size of everyone stays the same.

[yump]

Anux

See https://vlsiuniverse.blogspot.com/20...-with.html?m=1.

Higher clocks require spacing things apart to control thermal density, which leads to longer wires with more RC, which need to be driven by wider transistors (finfet width is quantized to integer number of fins), which need to be wider still to meet the tighter timing margin at high clock speed. And then those wider transistors present larger capacitance to whatever drives them, so might propagate width increase deeper into the design, or require another stage of buffering.

5+ GHz is a vicious circle of suck. A vicious human centipede, if you will.

[Anux]

Anux
Higher clocks require spacing things apart to control thermal density, which leads to longer wires with more RC, which need to be driven by wider transistors (finfet width is quantized to integer number of fins), which need to be wider still to meet the tighter timing margin at high clock speed. And then those wider transistors present larger capacitance to whatever drives them, so might propagate width increase deeper into the design, or require another stage of buffering.

I'm aware of the theories and am not denying it either. What I was raging on about is if AMD really made the transistors (gate distance etc.) smaller or just packed the same size transistors closer together.
I find it hard to believe that AMD wouldn't tell everyone if they were able to reduce the transistor size. In their slides they only talk about moving everything closer together.

[yump]

I'm aware of the theories and am not denying it either. What I was raging on about is if AMD really made the transistors (gate distance etc.) smaller or just packed the same size transistors closer together.
I find it hard to believe that AMD wouldn't tell everyone if they were able to reduce the transistor size. In their slides they only talk about moving everything closer together.

If they tell the synthesis tools things can be closer together, they will choose smaller transistors in marginal cases (wires that were *just* long enough to require a particular drive strength no longer will). Same with frequency target. It's not going to affect everything like a process shrink, but some transistors are definitely smaller.

[Jedibeeftrix]

Perhaps enough for a "Pro" version of current Steam Deck, but not for the new generation of device. For SD2 we should be looking at something like 6/8 ZEN5c + 10-16CU RDNA4 on N3. As Z1 Extreme demonstrates ZEN4 and RDNA3 are not that impressive in <15W mode. Dense cores and incremental GPU upgrade won't make much of the difference there, not sufficient for next gen anyway.

agreed, given the decision to re-spin the existing APU down to 6nm they obviously have plans to keep it going long enough to make a steamdeck 2 APU a big step-up in capability.