AMD Announces Zen 4C Cores Coming To Ryzen Laptops

[xorbe]

Article: "In particular, the Ryzen 3 7440U with its 8 cores / 8 threads"

The slide says 4 core / 8 thread?

[Anux]

if i remember correctly it was this article: https://www.semianalysis.com/p/zen-4...-to-hyperscale

It's not in there.

but just take your words and think about it: bigger tranistors or same sitze tranistors but closer together results in the exact same result you need more chip area for the same tranistors...

Your argument was about electrons passing not area.

also about the electron flow you need for the same result if your distance is higher between the tranistors the electrons cause more heat on the wire...

You know about what trace length difference we are talking about? That would be somewhere in the µm range. Also some traces are longer in the dense design to get around denser compute clusters.

[qarium]

It's not in there.

it is not in there for the amd side but for intel... they say to get the 6ghz goal intel is forced to make the transistors bigger.
then i did read it in other sources i read so many articles per day that i somettimes lose the source where i find something

i am 100% sure that i did read that zen4 has bigger tranistors for the higher clock speed goal and the zen4c has smaller tranistors similar to the ARM-mobile cpus like in the apple m1/2/3 design.

i search a source for you for this no problem.

Your argument was about electrons passing not area.
You know about what trace length difference we are talking about? That would be somewhere in the µm range. Also some traces are longer in the dense design to get around denser compute clusters.

the optimisations are done in very very very small steps and areas... in their business every µm count...

[qarium]

It's not in there.

I have another source for you: "he individual transistors in Zen4c are physically smaller"

https://videocardz.com/newz/amd-phoenix2-cpu-die-shot-featuring-zen4-zen4c-architectures-has-emerged

the quote is form a commend:

" Nathaniel Roland Stickley ponicad 2 months ago ChimpPokymonz is correct. Zen4 and Zen4c are identical except that the Zen4c was implemented using "high-density libraries" for the transistor design and layout whereas regular Zen4 uses high performance / high-clock speed libraries. In other words, the individual transistors in Zen4c are physically smaller and the software has laid them out differently on the die. Large transistors can carry more current without failing. The main functional difference is that Zen4 can reach higher clock frequencies."

and this is exactly my knowlege... the difference is the "high-density libraries" vs "high performance / high-clock speed librarie"

and thats the same reason why the 10nm intel tranistors can do 6ghz: "Large transistors can carry more current without failing. The main functional difference is that Zen4 can reach higher clock frequencies."

[qarium]

It's not in there.

and another source: "If the concept of Zen 4c were to be summarized: According to AMD’s CTO Mark Papermaster, the purpose of this core is to significantly increase the transistor density (and thus reduce its area) so that more of them can be crammed into a given area"

" Density increased thanks to physical design targetting lower clock speeds
The main difference from Zen 4 is that AMD has redesigned the physical implementation of the architecture and used libraries aimed at higher transistor density instead of libraries designed for high performance. Also, the provisioning for TSV (vertical wiring vias for connecting 3D V-Cache) has been eliminated, which also saved space on the chip. Overall, a CPU chiplet with 16 Zen 4c cores and 2×16MB L3 cache should still measure only 72.7 mm², while the area of a regular Zen 4 is 66.3 mm². So the silicon area has increased by less than 10% when doubling the number of cores (and the amount of L2 cache).
"

"According to the available images of the core, it seems that AMD has also changed the layout and placement of parts of the core on the chip. Apparently, the blocks are less partitioned and synthesis could “stuff” them closer together. This is probably because delineated partitions isolating individual blocks are meant to make it easier to test and verify CPU functionality on a new architecture, with Zen 4c as a reimplementation of one already existing being less sensitive to this. Zen 4c has only four such “partitions” (frontend, execution units, L2 cache and FPU/SIMD unit). This alone saves some space that was left unused in Zen 4, because the synthesis of the circuits couldn’t overlap the partitions in before."

"At the same time, standard block libraries that optimise for higher density and design that sacrifices the ability to achieve high clock speeds (which go well above 5 GHz for desktop Zen 4 processors) were used. High-speed design uses extra transistors and elements (or larger transistors) and many locations to improve the achieved clock frequencies. Zen 4c eliminates this, as it only expects or aims to run at significantly lower clock speeds. The resulting circuit can then be implemented in a smaller footprint. Different parts of the core are said to have their area reduced by up to 35–45%. This is while using the same 5nm node (TSMC N5). The key to this increase is believed to be mainly the simplification of the wiring (in the metal layers) between the transistors that results from the abandonment of high-speed design."

"It seems that the area of the L2 cache itself is one thing that has not been shrunk– its SRAM cells still have the same density and area – but its control circuitry has been reduced in size. However, some other SRAM blocks in the core logic have been made more dense, with AMD using 6T cells (made of six transistors) instead of 8T cells with eight transistors. 8T cells were previously used because of the dual-port feature (two sets of read/write wires can be connected to them), but TSMC has developed special 6T cells with pseudo dual-port functionality that can do this through double-pumping (two accesses happen sequentially in one cycle via one single interface). And Zen4c reportedly uses this technology."

https://www.hwcooling.net/en/big-little-by-amd-zen-4c-has-the-same-ipc-as-the-big-zen-4-architecture-analysis/

so i hope this source solve the mystery for you...

[ET3D]

It's not in there.

The article says: "a lower operating clock enables designers to squeeze signal paths closer together and improve standard cell density." There are likely other explanations there; I haven't read it fully. In any case looks like a good article.

[qarium]

The article says: "a lower operating clock enables designers to squeeze signal paths closer together and improve standard cell density." There are likely other explanations there; I haven't read it fully. In any case looks like a good article.

thank you yes i always try to light up the readers who read my posts.

if you find this one interesting read the other link i found to this other article is even better:

https://www.hwcooling.net/en/big-little-by-amd-zen-4c-has-the-same-ipc-as-the-big-zen-4-architecture-analysis/

it explained it in much more detail and i think it is the orginal source the most educated commenders get their info from.

[drakonas777]

still think a 5nm 8core Zen4c / 8CU RDNA3.5 APU would make a great steamdeck 2 chip.

Perhaps enough for a "Pro" version of current Steam Deck, but not for the new generation of device. For SD2 we should be looking at something like 6/8 ZEN5c + 10-16CU RDNA4 on N3. As Z1 Extreme demonstrates ZEN4 and RDNA3 are not that impressive in <15W mode. Dense cores and incremental GPU upgrade won't make much of the difference there, not sufficient for next gen anyway.

[qarium]

Perhaps enough for a "Pro" version of current Steam Deck, but not for the new generation of device. For SD2 we should be looking at something like 6/8 ZEN5c + 10-16CU RDNA4 on N3. As Z1 Extreme demonstrates ZEN4 and RDNA3 are not that impressive in <15W mode. Dense cores and incremental GPU upgrade won't make much of the difference there, not sufficient for next gen anyway.

lets say Valve only focus on 15watt mode because its a mobile device

then ZEN4c/ZEN5c would be a absolute must to get any performance per watt improvements.

also for a SteamDeck2.0 the Z1 Extreme has to many cpu cores and to less gpu cores and the real bottle neck is the
memory throughput.... lets say the Deck2.0 will stay on 128bit memory interface then this would result in only 2 known options;
option 1 you ignore the ram and add a 3D Cache to improve gaming performance for the SOC this already works well for the X3D cpus from AMD... a SOC would bring this performance uplift also to the GPU side.
if this is not an option for Deck2... then there is only one option left and this is DDR5 MRDIMMS with 17600MTs

https://www.tomshardware.com/news/amd-advocates-ddr5-mrdimms-with-speeds-up-to-17600-mts

MRDIMMS would double the memory throughput.
but keep in mind the SteamDECK2.0 want to save power in gaming and the X3D AMD CPUs shows you need this 3D cache technology to save power for gaming.
the Steam Deck zen2 SOC is made in 7 nm MOSFET node and because of mobile device on battery they should shink the die on
4nm or better 3nm...

lets say they do all of this then i think a Steam DECK 2.0 with double the performane at 15watt is possible.

Z1 Extreme and most benchmarks show we do not need 8 cores we maybe need 6 cores... and for the deck maybe 2cores with zen5 and 4cores zen5c ...

if we really have 17600MTs MRDIMMS then we can double the GPU CUs maybe RDNA4 instead of RDNA3

[billyswong]

So... are there any numbers / comparison from Zen3 to Zen4c to Zen4?