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AMD Announces Zen 4C Cores Coming To Ryzen Laptops

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  • AMD Announces Zen 4C Cores Coming To Ryzen Laptops

    Phoronix: AMD Announces Zen 4C Cores Coming To Ryzen Laptops

    We've been impressed with AMD Zen 4C cores with their initial appearance in Bergamo with the flagship EPYC 9754 and then over the summer with Siena for the likes of the EPYC 8324P(N) plus the EPYC 8354P(N) review soon. Today AMD is confirming what many had anticipated: Zen 4C cores will be coming to new Ryzen laptop SoCs.

    Phoronix, Linux Hardware Reviews, Linux hardware benchmarks, Linux server benchmarks, Linux benchmarking, Desktop Linux, Linux performance, Open Source graphics, Linux How To, Ubuntu benchmarks, Ubuntu hardware, Phoronix Test Suite

  • #2
    Nice,
    Intels E-cores have only 1,5 mm² (4C have 2,5 mm²) but are also much slower and lack many features. Contrary Intels P-core area is 5,5 mm² while Zen4 needs only 4 mm². Ok AMD uses a much denser TSMC process vs Intels 10+++++ but still the difference is huge. It may be a sacrifice to their 6 GHz clock goal.

    I wouldn't mind a 4C only mobile chip, if it's cheaper.

    Intel area analysis: https://www.semianalysis.com/p/meteo...d-architecture
    Last edited by Anux; 02 November 2023, 10:01 AM.

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    • #3
      I don't understand: other than lower boost clocks, what's actually different about these cores? With AVX-512 and SMT, what's actually sacrificed? And, what's preventing these cores from boosting higher?
      Last edited by schmidtbag; 02 November 2023, 10:29 AM.

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      • #4
        Originally posted by schmidtbag View Post
        I don't understand: other than lower boost clocks, what's actually different about these cores to make them use up so much less die space? With AVX-512 and SMT, what's actually sacrificed? And, what's preventing these cores from boosting higher?
        IF I understand correctly it is cache size that is sacrificed from earlier benmarks of the ZEN 4c.

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        • #5
          Originally posted by schmidtbag View Post
          I don't understand: other than lower boost clocks, what's actually different about these cores to make them use up so much less die space? With AVX-512 and SMT, what's actually sacrificed? And, what's preventing these cores from boosting higher?
          50% less L3 cache per core. Imagine programming the scheduler for a supposed Zen4+C+X3D CPU

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          • #6
            Originally posted by schmidtbag View Post
            I don't understand: other than lower boost clocks, what's actually different about these cores to make them use up so much less die space? With AVX-512 and SMT, what's actually sacrificed? And, what's preventing these cores from boosting higher?
            Less L2 cache is one big point and a denser layout of the compute part (which hampers high frequencies).

            L3 cache is not even in the area computation of these slides. But lower frequencies result in less mem bandwidth and fewer cache misses, therefore a core designed for lower clocks doesn't need the same amount of cache.

            Edit: L2 is the same in all core variations, 1MB per core, another link: https://www.semianalysis.com/p/zen-4...-to-hyperscale
            Last edited by Anux; 02 November 2023, 10:40 AM.

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            • #7
              I'm really interested to see how Zen4C's power efficiency holds up. It still looks ok paper like space efficiency. Not that I'm against that. They seem to be suggesting it's also power efficient. I'd love if they can pull that off.
              I actually thought cache really helps your power efficiency, but maybe 4C has some extra tricks up its sleeve or perhaps it just has a more efficient power table and clock limit. EDIT: they imply the smaller size itself will help efficiency on its one.

              I'll take 4P8C over 8P any day in a laptop as long as we aren't giving up power efficiency or instruction sets. AVX is super important with the fact that encryption is everywhere. I prefer LUKs wherever my OS is installed.

              The benefits of heterogenous CPUs are pretty clear.
              Last edited by Mitch; 02 November 2023, 10:40 AM.

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              • #8
                Originally posted by skeevy420 View Post
                50% less L3 cache per core. Imagine programming the scheduler for a supposed Zen4+C+X3D CPU
                Yeah kind of odd how AMD went the opposite direction.
                Makes me wonder if they'll make a CPU with a group of C cores, standard cores, and X3D cores.

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                • #9
                  Originally posted by Mitch View Post
                  I'm really interested to see how Zen4C's power efficiency holds up. It still looks ok paper like space efficiency. Not that I'm against that. They seem to be suggesting it's also power efficient. I'd love if they can pull that off.
                  The only reason it seems to be more power efficient is because of lower clocks, run a normal Zen 4 at the same 4C clocks and efficiency should be very similar.

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                  • #10
                    When paired with RDNA3 these chips will make great mid-range/budget candidates. Hopefully the next generation E-line of ThinkPads will ship with these.

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