Originally posted by qarium
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But they're also using tiles for the same reason that AMD does. The SOC and I/O dies are on 6nm because it's an older, more mature process, the does contain PHYs which tend not to shrink as well, and the hardware blocks on them don't need clock speeds to be as aggressive as a GPU or CPU. They can also re-use these tiles on other designs.
Originally posted by qarium
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In other words, the GPU tile is quite a bit smaller than the A380.
The A380 annotated die shot is on the right. So just imagine cutting off the right side and the bottom then reconfiguring what's left to be more verticle, then shrink it to N5. That would be the GPU tile.
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