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Linux 6.5 Preps For IBM POWER's "DEXCR"

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  • Linux 6.5 Preps For IBM POWER's "DEXCR"

    Phoronix: Linux 6.5 Preps For IBM POWER's "DEXCR"

    Patches being queued ahead of the upcoming Linux 6.5 kernel merge window prepare initial support for DEXCR that is found in recent Power ISA specifications...

    Phoronix, Linux Hardware Reviews, Linux hardware benchmarks, Linux server benchmarks, Linux benchmarking, Desktop Linux, Linux performance, Open Source graphics, Linux How To, Ubuntu benchmarks, Ubuntu hardware, Phoronix Test Suite

  • #2
    These PowerPC cpus require a car radiator...

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    • #3
      Power10 is really not a successfull product. i hope power11 is as opensource friendly again as power9
      Phantom circuit Sequence Reducer Dyslexia

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      • #4
        Originally posted by qarium View Post
        Power10 is really not a successfull product. i hope power11 is as opensource friendly again as power9
        It seems to be more successful than POWER9 in all respects so far. Or did you just mean open source friendliness ? If so that's fine and I agree Power10 is behind POWER9 there but the term "successful" generally refers to business success and in that regard Power10 seems to have worked out well for IBM.
        Last edited by bridgman; 20 June 2023, 10:58 PM.
        Test signature

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        • #5
          Originally posted by bridgman View Post
          It seems to be more successful than POWER9 in all respects so far. Or did you just mean open source friendliness ? If so that's fine and I agree Power10 is behind POWER9 there but the term "successful" generally refers to business success and in that regard Power10 seems to have worked out well for IBM.
          if business success means that people stop talking about you in a positive way??...
          believe it or not but a power system was on my shopping list in the past but with power10 i plain and simple set this plan on hold.
          ok mr. bridgman can you exaplain to me why power 10 is more successful than power9 ?
          can you explain to me how power 10 worked out well for IBM ?

          and i get the point they have old customers trapped in their ecosystem who are forced to buy power products...

          but i am not trapped and to me it looks like even AMD is copy the ARM server CPUs with their non-Hyperthreading 128core ZEN4c cpu...

          i did write you this in the past you know it i do not like hyperthreading on high-core count cpus... over 32/64cores hyperthreading is practically death.

          so tell me why should i buy Power10 if i can buy a ARM AmpereOne 192 core cpu instead ?

          and according to this article: https://www.semianalysis.com/p/zen-4...-to-hyperscale

          the rationality for IBM power products are a absolute minority of user cases only the case if you are trapped in the ecosystem and you are trapped on outdated code to run what force it to single-thread performance instead of multicore performance.

          AMD cpus have 2 way hyperthreading IBM power cpus have 4 way hyperthreading the new zen4c 128core cpu you can buy it without hyperthreading the "ARM AmpereOne 192 core" does not have hyperthreading.

          in my point of view hyperthreading only eats up your ram 2 way hyperthreading eats up to double the amount of ram and 4 way hypertheading is even worst.

          a "ARM AmpereOne 192 core cpu" does need less ram than the normal 128core zen4c cpu with hyperthreading...

          cloud customers already successfully flee the x86-64 cpus because of hyperthreading gives them fake cpus without performance.

          on ARM you always get the full performance per core.
          Phantom circuit Sequence Reducer Dyslexia

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          • #6
            Originally posted by qarium View Post

            if business success means that people stop talking about you in a positive way??...
            believe it or not but a power system was on my shopping list in the past but with power10 i plain and simple set this plan on hold.
            ok mr. bridgman can you exaplain to me why power 10 is more successful than power9 ?
            can you explain to me how power 10 worked out well for IBM ?

            and i get the point they have old customers trapped in their ecosystem who are forced to buy power products...

            but i am not trapped and to me it looks like even AMD is copy the ARM server CPUs with their non-Hyperthreading 128core ZEN4c cpu...

            i did write you this in the past you know it i do not like hyperthreading on high-core count cpus... over 32/64cores hyperthreading is practically death.

            so tell me why should i buy Power10 if i can buy a ARM AmpereOne 192 core cpu instead ?

            and according to this article: https://www.semianalysis.com/p/zen-4...-to-hyperscale

            the rationality for IBM power products are a absolute minority of user cases only the case if you are trapped in the ecosystem and you are trapped on outdated code to run what force it to single-thread performance instead of multicore performance.

            AMD cpus have 2 way hyperthreading IBM power cpus have 4 way hyperthreading the new zen4c 128core cpu you can buy it without hyperthreading the "ARM AmpereOne 192 core" does not have hyperthreading.

            in my point of view hyperthreading only eats up your ram 2 way hyperthreading eats up to double the amount of ram and 4 way hypertheading is even worst.

            a "ARM AmpereOne 192 core cpu" does need less ram than the normal 128core zen4c cpu with hyperthreading...

            cloud customers already successfully flee the x86-64 cpus because of hyperthreading gives them fake cpus without performance.

            on ARM you always get the full performance per core.
            ouch.

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            • #7
              I'm a little confused, because protection against return oriented programming and side channels attacks are not related, other than having to do with security.

              So while Power might put enabling bits next to each other in control registers, I tried to find out what Power is actually doing to defend against RoP: are they using an approach similar to ARM with encrypted tags for compiler identified jump/branch targets in the high address bits or are they using a shadow stack register like x86. And the chapter reference only seems to deal with side channel settings in the context of hypervisors, not with RoP defense.

              A deeper link or even a feature article on the state of RoP defenses in the various architectures would be rather nice to have.

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