AMD Zen 5 "Znver5" CPU Enablement Merged For GCC 14

[phoronix]

Phoronix: AMD Zen 5 "Znver5" CPU Enablement Merged For GCC 14

Back in February AMD posted GCC compiler enablement support for Zen 5 with the new "znver5" target ahead of launch. Since then it's been rather quiet and nervous not seeing this support merged ahead of the upcoming GCC 14 stable release, but this morning it's finally happened: the AMD Zen 5 processor enablement has been merged to GCC Git in time for the GCC 14.1 stable release that will be out in the coming weeks...

https://www.phoronix.com/news/AMD-Zen-5-Znver5-Merged-GCC14

[avis]

There's zero Zen 5 specific code in the patch. It's just for the looks, the actual code to properly support Zen 5 will be released later:

+/* This table currently replicates znver4_cost table. */
+struct processor_costs znver5_cost = {

[elbar]

some interprocessing language in the working or is asm or wasm still the best choice for LISP/Haskell development in Blue Chips corporations? Google is watching

[david-nk]

I was going to ask if they ever update these cost tables... but yeah, they do.
Interestingly enough, the costs are consistently higher for znver4 compared to znver3 to the point that I wonder how Zen 4 manages to be faster at all... but I guess the upgraded cache does a lot.

128/256-bit SSE register load: 6 -> 10
256-bit SSE register store: 8 -> 12
FADD/FSUB/FMUL: 5 -> 7
FSQRT: 10 -> 25
DIVSS: 10 -> 13
SQRTSS: 10 -> 15
etc.

[reba]

I was going to ask if they ever update these cost tables... but yeah, they do.
Interestingly enough, the costs are consistently higher for znver4 compared to znver3 to the point that I wonder how Zen 4 manages to be faster at all... but I guess the upgraded cache does a lot.

128/256-bit SSE register load: 6 -> 10
256-bit SSE register store: 8 -> 12
FADD/FSUB/FMUL: 5 -> 7
FSQRT: 10 -> 25
DIVSS: 10 -> 13
SQRTSS: 10 -> 15
etc.

I don't exactly know how these cost-tables work but when they are comparing costs with each other that could mean those instructions did not get slower but all the other faster.

[david-nk]

I don't exactly know how these cost-tables work but when they are comparing costs with each other that could mean those instructions did not get slower but all the other faster.

Yeah, these tables aren't entirely clear, so I cross checked with the Agner Fog instruction tables. While the latencies more or less correspond to the costs in the GCC tables, you can see that while latencies went up, throughput is often unchanged or even slightly higher for Zen 4, for example for the DIVSS instruction. Reciprocal throughput went from 3.5 to 3 for that one. So that would definitely explain why Zen 4 can still be faster overall.

[drhoho]

There's zero Zen 5 specific code in the patch. It's just for the looks, the actual code to properly support Zen 5 will be released later:

+/* This table currently replicates znver4_cost table. */
+struct processor_costs znver5_cost = {

I think the point was by adding this stub now, actual Zen 5 specific code could be implemented with patches later. Otherwise, they would have to wait for the next GCC rev.