Partial SMT Enablement Support Lands For Linux 6.6

[phoronix]

Phoronix: Partial SMT Enablement Support Lands For Linux 6.6

As part of the "smp/core" changes that were merged last week for the Linux 6.6 kernel, partial SMT enablement landed for processors that support more than two threads per physical core to allow greater run-time control over just how many threads to enable...

https://www.phoronix.com/news/Linux-6.6-Partial-SMT-Enable

[ezst036]

Intel must have an internal patch somewhere that they use.

They just recently demoed a non-x86 8 core RISC chip that can process 66 threads per core.

[sophisticles]

Intel must have an internal patch somewhere that they use.

They just recently demoed a non-x86 8 core RISC chip that can process 66 threads per core.

https://wccftech.com/intel-discloses-8-core-528-thread-cpu-based-on-risc-architecture-66-threads-per-core/

[WorBlux]

Intel must have an internal patch somewhere that they use.

They just recently demoed a non-x86 8 core RISC chip that can process 66 threads per core.

The are made for for a certain type of graph traversal that is doing a memory load or branching every 3-6 instructions. Where 1-2 threads you'd sit idle 98% of the time, and a GPU would choke on too many instruction branches.

[cb88]

The are made for for a certain type of graph traversal that is doing a memory load or branching every 3-6 instructions. Where 1-2 threads you'd sit idle 98% of the time, and a GPU would choke on too many instruction branches.

That makes a lot of sense, given memory latency to system memory is around 80-150 cycles, if you have 66 threads you can keep the execution engine busy so long as several are serviced per cycle it can keep a fairly wide execution engine busy. Such a system is usually very undesirable for interactive use though. Also the execution engine can potentially get picky and only service threads that have the most data available etc...