ARM Launches "Facts" Campaign Against RISC-V

[Weasel]

A RISC-like uop is what an Intel CPU executes, which is done by translating the x86 opcode in an internal, fixed width format.
If its a short loop it will just execute those uops from a cache and not look at the x86 opcode.

You didn't get it. I can make claims too: a CISC-like uop is what an Intel CPU executes.

I was asking about what exactly is a RISC-uop. You know, giving me actual checkpoints I can verify myself and see what exactly makes an uop "RISC". It must have something to do with "reduced" though, since it's the first letter in the acronym, after all. Saying "separate load/store uops" is not RISC because I fail to see how that has anything to do with anything being "reduced" when it, in fact, adds new upos / instructions.

Because you see, the core is not RISC. It's RISC cores that are often more CISC-like than the actual ISA (due to fuse and other optimizations). It's not x86 that has a RISC core, it's modern RISC CPUs that have a CISC core, to be able to compete.

Typical RISC traits are a small number of instruction formats, but CPU's can have alot of instructions. Its the same as saying that x86 is not truly CISC, as they often use accumulator "a = a + b" which will result in additional instructions copying the state of a. How is this CISC (if this means having tons of instructions), did they changed the definition, and set out some alien reptiloids to rewrite all documents defining CISC (similar like you claim with RISC)?

I honestly have no idea what you're trying to say here, sorry.

CISC = complex, specialized instructions. AES instructions, CRC32, PDEP, PEXT, POPCNT, etc all of these are complex, specialized instructions in x86 CPUs (and many, many others).
RISC = reduced amount of instructions, typically implementing basic stuff only, because everything else can be implemented in terms of these reduced instructions.

RISC cannot have those type of complex instructions, period.

The arithmetic instructions are way simpler to implement than allowing various sources, targets and requiring different instruction formats. A good indication for that is pipeline length, further complicating stuff like Out-of-order processing and making heavy branch prediction necessary to avoid costly flushes.
Also, using 3-register OPS simplifies the design despite being more flexible.

Branch prediction is used in every modern CPU that aims at performance, has nothing to do with CISC/RISC.

On the contrary to what you stated, 3-register operands complicates the CPU core, because you need more wiring. It simplifies the compiled code (or ISA), not the core.

Thats a weird opinion, look around, the last hold-over with CISC is x86. GPUs are RISC, DSPs are RISC, embedded controllers are RISC, mobile CPUS are RISC, micro controllers are RISC.

But most of them are not RISC.

Why don't you just redefine RISC as "electrical component that does processing" and then guess what? Everything is RISC!

[AndyChow]

A general policy is to never comment on your competition. I makes you look smaller and petty. Since ARM has never had an ounce of interest in supporting the graphical drivers, even as blobs, for linux, I hope they slowly see Risc-V take them over, year by year.

[LaeMing]

There may only be one expensive dev board available for general use, but between Nvidia and Western Digital, I suspect ARM may already be wincing at lost future licensing revenue.

[oiaohm]

I honestly have no idea what you're trying to say here, sorry.

CISC = complex, specialized instructions. AES instructions, CRC32, PDEP, PEXT, POPCNT, etc all of these are complex, specialized instructions in x86 CPUs (and many, many others).
RISC = reduced amount of instructions, typically implementing basic stuff only, because everything else can be implemented in terms of these reduced instructions.

RISC cannot have those type of complex instructions, period.

This is where lines between CISC and RISC get mixed up.

https://fuse.wikichip.org/news/1068/isscc-2018-mits-low-power-hardware-crypto-risc-v-iot-processor/

Risc-v the risc instruction set allows giving commands to accelerators.

https://content.riscv.org/wp-content/uploads/2017/12/Wed1612_linear_algebra_Steffl.pdf

Really complex instructions is in the accelerator above far past what CISC does.

Please note the linear algebra accelerator is not cisc either it is what is called programmed logic. Particular accelerators using CISC just gets in the way as well.

x86 attempts to be CISC. Risc-v core is risc with accelerators done in programmed logic or CISC or what ever system suits that task best.

I can understand arm being worried. Risc-v is going a very different model.

Also Weasel it would pay for you to go have a read what is included in the risc instruction set of risc-v. Majority of code on a risc-v runs in the risc instructions.

Advantage of risc is processing core can be kept a lot smaller than a CISC core. Accelerators can be share between cores.

Remember size is a factor for top speed. Speed of electricity though silicon is fairly much a constant.

Vector instructions in riscv is not CISC its not exactly risc either.

https://riscv.org/wp-content/uploads/2016/12/Wed0930-RISC-V-Vectors-Asanovic-UC-Berkeley-SiFive.pdf

The question risc-v asks is really choosing risc/cisc only the right thing? Or should have cpu designs always have been mixed. Programmable logic is a type we have highly overlooked. Risc core controlling programmable logic is turning out quite decent in performance.

[GI_Jack]

Is it just me or ARM seems to be worried a lot for something that is practically non existent.

Not really no. WD just released a HD with a MIPS-V chip in it. Because of the lack of licensing fees, RISC-V is already attractive for low end embedded ASICs like controllers, because it reduces the price even further.

So while you won't see a RISC-V in cellphones anytime soon, the lower end ARM chips are in danger. Also, say goodby to ARC as well.

[coder]

who would pick a middle ground that satisfies nobody?

Perhaps you're unaware that Western Digital has gotten behind RISC-V, in a big way. Even if it's not the fastest architecture, it makes a lot of sense for high-volume, low-margin applications. WD ships literally billions of cores/year, so they're understandably sensitive to licensing fees.

[coder]

However, due to the CISC nature of the x86(_64) instruction set, a large number of transistors must now be dedicated to elaborate decoding logic, regardless of whether they target a low-power design point or a maximum-throughput. They have no choice if they want backwards compatibility.

I agree with the power implications of decoding such an unwieldy ISA like x86-64.

It's probably noteworthy that the Atom line of cores has stopped at SSE (although it's been picking up some non-vector extensions). This probably isn't enough to save them in decoder complexity, but more to do with not wanting to burn die space on 256-bit+ registers and the wider pipelines that would justify it.

[coder]

between Nvidia and Western Digital, I suspect ARM may already be wincing at lost future licensing revenue.

Nvidia wasn't using ARM in the way they're now using RISC-V - that was already a custom core. But their adoption of RISC-V does add more credibility to it.

[pal666]

Yeah we can all see, after 13 years, how Windows is completely dead with its 90% market share on the desktop.

desktop is tiny shrinking market
windows is dead on much larger smartphone market, and ms lost many billions trying to keep windows in 2% share range
windows is dead or irrelevant on any market besides desktop
on desktop ms is abusing monopoly, but even there the only growing segment is linux (chromebooks)

[pal666]

Not as good as a CISC CPU (for performance)

you are delusional
"cisc" does not mean "performance"
"many transistors" means "performance", that is what differentiates intel cpus from arm
current fastest supercomputer does not employ cisc cpus (or gpus)