AMD Queues Its First Batch Of AMDGPU Changes For Linux 5.9: Sienna Cichlid + More

[caligula]

The fact that RDNA1 has about 30% higher ILP than GCN4 is in my opinion an indication of the fact that x86 CPU architectures are somewhat closer to theoretical ILP limits than GCN4&RDNA1 GPU architectures, and thus it is harder to increase ILP by 1% in CPUs than to increase ILP by 1% in [AMD] GPUs.

CPUs less often deal with vector values and the apps have more data dependencies and lower amount of ALU operations vs control logc. Using vector instructions introduces some overhead and can't be applied everywhere even if some vector instructions get 100% speedup thanks to doubling of registers sizes. Moreover, yeah, the operating frequencies are higher, the pipeline is a result of decades of optimizations.

[pal666]

I am ready to accept a defeat if you post additional _reliable_ hardware configuration data about the next GPU. The IPC (instructions per clock) compared to Navi1 would be a quite useful datapoint ...

do you see ipc for any other card in kernel patches?