Originally posted by vladpetric
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Intel Rolls Out 10nm Pentium/Celeron CPUs, Previews Rocket Lake
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Originally posted by coder View PostThey could still split them in half and execute them as 2x 128-bit parts. Didn't AMD do that in Zen1? I know Pentium did that with SSE, in the Pentium 4.
In terms of area, AVX bloats the register file, but I wonder if that's even enough to bother about.
Anyway, let's not forget this is a 10-way core with 6-wide decode! So, we're not exactly talking about a microcontroller or IoT core. And its ancestors had SSE/SSE2 going at least as far back as the 22 nm days, so you'd expect at least basic AVX/AVX2-support wouldn't be completely off the table.
In case you missed it: https://en.wikichip.org/wiki/intel/m...t#Architecture
Sure, they could split them into 2x 128 bits, but then you could also just be using regular SSE42 (AMD has a few instructions that work on their early processors, but performance sucks to the point that it's not worth using the specialization; my main beef is with pext/pdep)
Look, you're generally making good points, I don't mean to nitpick.
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Originally posted by Space Heater View PostRHEL 9 is doing this, but when did Fedora decide to switch to that?
Here's the article: https://www.phoronix.com/scan.php?pa...86-64-v2-Plans
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Originally posted by atomsymbol
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Originally posted by coder View PostNot exactly. Fedora is drawing the line at "near-Nehalem", which is the ISA level before AVX and a bar which these definitely clear.
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Originally posted by Inopia View PostTBH they kind of skipped the 5th gen by not really releasing more than token Broadwell dektop offerings.
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Originally posted by vladpetric View PostYou know, there is actually a way to test it out to some degree. With an AMD Ryzen retail, on an x570 pro mobo or similar, you try vanilla rowhammer (not ECCploit) ... If you're successful at vanilla rowhammer, it means that ECC doesn't work. If you're not successful ... well, you haven't really learnt much.
Another option is to try an ECC DIMM that's known to be defective.
Probably the best (and most difficult) is to use the kernel-support for injecting faults, and see if they're reported. A guy in the RealWolrdTech thread where Linus posted was talking about this, but hadn't updated with his relults, last I checked.
BTW, someone posted a link to an article showing that rowhammer is still possible (though much more difficult), even with ECC. But, what should be a lot easier is to try rowhammer and see if it causes an ECC event. That's all you need -- for it to trigger a correctable error. However, if your ECC support is indeed broken, then I guess you'd get a successful rowhammer, instead.
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Originally posted by vladpetric View PostYeap, unfortunately they are indeed small cores - the single threaded performance of those is pretty poor compared to even a Pentium.
Considering its power envelope, that's substantial.
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