Intel Begins Teasing Their Discrete Graphics Card

[Weasel]

start here https://en.wikipedia.org/wiki/Long_mode and return with explanation of why do you need both 32 and 64 bit libs on 64bit host

And that has to do with the "x86 is the entire lineup" how exactly?

Maybe you should start here https://en.wikipedia.org/wiki/X86.

Too obvious for you.

but x86 is not tied to avx, so avx is not part of x86

What kind of ass backwards logic is that?

x86 is not tied to AVX, since there are x86 CPUs without AVX.
But AVX is tied to x86, and that's perfectly normal logic.

lol, you can have even 8 if you don't need stack
In reality you're full of shit.

You can't, because of a thing called exceptions and signals (on Linux/Unix) -- that's why the "Red Zone" exists on x86-64, to guarantee it's not touched by signal handlers, which clearly need a valid stack pointer. Even on Windows, it needs a valid stack for any exceptions (which might be caused by external processes). Invalid stack pointer at any moment = risk of application crash randomly, depending on external factors.

So no, you're still full of shit and don't know shit. You can't even make compilers use the stack pointer for "other stuff", but you CAN make the other two registers you whined about, in fact they're the fucking default (the options I gave you) so take a piss.

[Weasel]

of course they do. just compare latest power cpu with earliest x86, moron.

No compare latest x86 Xeon with earliest power cpu, moron.

[Weasel]

There's not much here besides name-calling and possibly willful misunderstanding. Sorry, I'm not really down for that.

Maybe. I thought you were complaining about Intel's choice of x86 for their GPUs being bad, as in you would have picked another CPU (not GPU) arch instead (e.g. ARM).

Thing is they wanted a "general purpose CPU" on it, not a GPU ISA. This has nothing to do with x86. So if you want to blame them, do it for that decision, not "because it's x86".

Okay, if you're going to win on a technicality, I guess you have it.

He doesn't win anything. Read the (very carefully named) "x86" article on Wikipedia.

[coder]

What GPU engineers call a core is what CPU engineers call a pipe.

In a CPU context, pipelines refer to a systolic processing construct and that applies equally to vector and scalar operands.

So, I just say "SIMD lane". I hope that's unambiguous enough. And I assume it was the GPU marketing departments that took a liking to equating SIMD array elements with "cores", since it really bends the traditional definition of a core and only serves to make their chips sound that much more impressive.

Below I add a translation dictionary between CPU and GPU terminology

Thanks for contributing, but perhaps I'll have a go.

CPU	Nvidia GPU	AMD GPU
core	Streaming Multiprocessor (SM)	Compute Unit (CU)
thread	warp	wavefront
SIMD lane (i.e. hardware construct)	core	stream processor
SIMD data element (i.e. logical construct)	thread	work item

[creative]

I figured people knew this, but Larrabee was an unreleased predecessor to what would later be released as Xeon Phi:

https://en.wikipedia.org/wiki/Xeon_Phi

And that's where it ended, too.

https://www.anandtech.com/show/13111...nights-landing


Intel's latest server roadmaps show no true successor to the 7200 series. In the HPC segment, they show it being succeeded by a seemingly standard Cascade Lake Xeon-SP server processor.

https://www.anandtech.com/show/13119...sp-due-in-2020

Maybe later than 2020 then, no idea of how long a first development cycle for new tech like this will take. iGPU's hmmm... Maybe their plan is as such to strap existing iGPU tech to a board, without the thermal inclusion of a regular CPU such a thing might travel quite far.

Perhaps I state the obvious a little too much.

Too much speculation, it could very well never see the light of day.

[RussianNeuroMancer]

i didn't say anything about arm and certainly arm isn't tied to mali. just plug amd vidocard into pci slot like with others.

No laptop vendor going do this with ARM-based laptops, as there is no games, so no point in dGPU.

but you have glaring omission in your list: i guess freedreno is more production quality than v3d

Good to know! Support of Snapdragon's laptop variants can't come soon enough

[juanrga]

x86-64 is not x86. x86-64 cpus are compatible with x86 because they can switch into mode which understand parts of x86 spec. any cpu can be designed to do that.(if license is available that is)
avx is not part of x86 or x86-64. it is a separate extension and any cpu arch can have vector extensions.

Some people uses x86 to refers only to the original 16-bit and 32-bit ISAs and uses the terms x86-64 or x64 for the 64-bit extension.

Others use the term x86 to embrace everything: e.g. x86-32 and x86-64 are part of a x86 superset in their view.

AVX is an extension to x86. AVX cannot be used with ARM or Power CPUs.

[juanrga]

Interesting, but I still don't see how a 3k "pipeline" is anywhere close to Xeon Phi. Was the Phi's pipeline length even published? Phi is at most ~5x slower (but usually between 2x to 3x) anyway, and since it's designed like a general purpose CPU more or less (with a large cache and all) -- and that's according to Nvidia's "statistics".

Intel Phi 7290: 72 CPU cores @ 1500MHz. Max performance 3456 GFLOPS

Nvidia P100: 3584 CUDA 'cores' @ 1328MHz. Max performance 4760 GFLOPS

The GPU is advertised as 3k cores accelerator, but is not 40x faster than the 72 cores Phi CPU, because what Nvidia call cores is not what CPU engineers call cores. Per former table, what Intel engineers call a core is what Nvidia engineers call a SM (Streaming Multiprocessor). And the Nvidia P100 has 56 SM cores. So

Intel Phi 7290: 72 CPU cores @ 1500MHz. Max performance 3456 GFLOPS

Nvidia P100: 56 SM cores @ 1328MHz. Max performance 4760 GFLOPS

Clock-for-clock each SM core is about so powerful like two Phi cores. Regarding performance we can equate an Nvidia SM with an Intel tile

56 SM ~ 36 tiles

Point is that other CPUs (general purpose) would fare way worse.

Fujitsu line of supercomputers built around general purpose CPUs say otherwise. The K-computer was very good and continues being good despite being outdated. The post-K promises to be the first exascale supercomputer, and it is built around ARM CPUs with 512bit SIMD units.

[juanrga]

Xeon Phi has many problems. Pipeline length in a Xeon Phi is in fact 6 yes under half of the normal 14. Each core is pure in-order single instruction CISC. So unless you optimise your code well Xeon Phi is going to perform like total garbage. Yes you need to use the CISC instructions that fill all the cpu micro op ports the cores have no smarts.

Xeon Phi has many problems, but Knights Landing cores hit enough frequency for HPC stuff, they are out-of-order cores and can execute up to four threads simultaneously (SMT4).

[creative]

IBM's Summit is sailing the known seas and is now the worlds most powerful supercomputer powered by Nvidia.

That is at least news to me.