Linux 6.10 x86 Instruction Decoder Prepares For APX & Other New Intel Instructions

[phoronix]

Phoronix: Linux 6.10 x86 Instruction Decoder Prepares For APX & Other New Intel Instructions

The performance events updates were submitted today for the ongoing Linux 6.10 kernel merge window. This pull adds support for Advanced Performance Extensions (APX) and other new Intel CPU instructions to the x86 instruction decoder...

https://www.phoronix.com/news/Linux-6.10-x86-APX-Decode

[coder]

Has anyone heard (or have a very well-reasoned conjecture on) what CPU will be first to implement APX? I'd bet it's not before Panther Lake (2025). Perhaps Lunar Lake (Q4 2024?), but I think that might be a stretch.

Definitely excited for it, though. It's going to have a much bigger impact on everyday desktop & server computing workloads than yet-another-round of AVX-type instructions.

[timofonic]

Any hopes AMD is going to implement APX too?

[edxposed]

Any hopes AMD is going to implement APX too?

AMD is always on Intel's ass.

[geerge]

Any hopes AMD is going to implement APX too?

No doubt, but when. intel would've disclosed the development to them as late as possible for competitive advantage, so maybe not even in zen6. Designs are in the pipe for years.

[timofonic]

No doubt, but when. intel would've disclosed the development to them as late as possible for competitive advantage, so maybe not even in zen6. Designs are in the pipe for years.

Wouldn't microcode update be enough to implement it? If not, what's so special behind it?

[duby229]

Wouldn't microcode update be enough to implement it? If not, what's so special behind it?

No, a microcode update won't work. This is an architecture change. It adds new registers and they are in a different format.

https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html

[debrouxl]

Modern processors use register files, so if there are enough spare registers, it might be possible to implement a subset of APX through a microcode update. However, a full-featured, maximally efficient implementation certainly needs a micro-architecture specifically designed with APX changes in mind, indeed.

[coder]

intel would've disclosed the development to them as late as possible for competitive advantage, so maybe not even in zen6. Designs are in the pipe for years.

I do think you could probably stuff APX support into a CPU that's already pretty far along in its development cycle, assuming the changes can be primarily constrained to the instruction decoders.

Modern processors use register files, so if there are enough spare registers, it might be possible to implement a subset of APX through a microcode update.

No, from what little I've gleaned about microcode and instruction decoders, it's not feasible to retrofit this in a CPU that totally wasn't designed for it. As you point out, even if you could, it wouldn't be terribly efficient.

A much better way to retrofit older CPUs would be just to trap the REX2 prefix and use a JIT translator to execute the code at near-native speed.

[TheLexMachine]

Has anyone heard (or have a very well-reasoned conjecture on) what CPU will be first to implement APX? I'd bet it's not before Panther Lake (2025). Perhaps Lunar Lake (Q4 2024?), but I think that might be a stretch.

Definitely excited for it, though. It's going to have a much bigger impact on everyday desktop & server computing workloads than yet-another-round of AVX-type instructions.

It will likely land in Xeon CPUs first, as it's primary purpose is for compiling/recompiling code on the new hardware, to make it run more efficiently on the older hardware that is already in use in enterprise and consumer markets. After that, who knows.