AMD Announces Milan-X 3D V-Cache CPUs, Azure Prepares For Great Upgrade

[Paradigm Shifter]

AMD did also tease ROCm 5.0 is on the way... Besides adding MI200/Aldebaran support there, their open-source compute stack will hopefully see official RDNA/RDNA2 GPU support with ROCm 5.0.

At this point, I'll believe it not only when I see it, but when I have successfully installed it on an RDNA2 GPU system and run code.

The proof is in the pudding.

[smitty3268]

MI200 feels odd. It is dual GPU on board card and it is compared vs single chip A100, that on top of that has some unique properties like ability to split into multiple instances. A100 that is already aging, and is single chip and only having between 1.4x to max 2.4x in aplications better performance on newer process node with still subpar CUDA support is .... questionable.

Also I don't see information about power draw what in such utilization is very important for example 9 out of top10 in Green500 is Nvidia GPU driven.

560W I believe.

It's certainly an interesting product. It's not quite 1 GPU or 2 GPUs.

AMD doesn't really have any choice but to compare to the A100. They don't have access to NVidia's next-gen chip.

[Mike Frett]

I am kind of worried about Zen after the latest Intel launch...

Not me. Intel still sacrifices security for performance and several cloud providers say Intel runs too hot and have opted out of Intel for now.

[lejeczek]

phoronix Such a shame those number you cannot reveal and many are itching to see, I'm. Can we bribe you?

[Linuxxx]

Not me. Intel still sacrifices security for performance and several cloud providers say Intel runs too hot and have opted out of Intel for now.

Please show me where Intel still sacrifices security for performance?!

On the other hand, you seem to forget about this:

We discover timing and power variations of the prefetch instruction that can be observed from unprivileged user space. In contrast to previous work on prefetch attacks on Intel, we show that the prefetch instruction on AMD leaks even more information. We demonstrate the significance of this side channel with multiple case studies in real-world scenarios. We demonstrate the first microarchitectural break of (fine-grained) KASLR on AMD CPUs. We monitor kernel activity, e.g., if audio is played over Bluetooth, and establish a covert channel. Finally, we even leak kernel memory with 52.85 B/s with simple Spectre gadgets in the Linux kernel. We show that stronger page table isolation should be activated on AMD CPUs by default to mitigate our presented attacks successfully.

At least get your facts straight when spreading FUD...

[GrayShade]

I like silent and efficient PC: even do not use PBO on my newly acquired 3700X, so it's ~90W at max load, but still maintains ~4GHz all core.

How much does your whole system use? I've been pretty disappointed with the power usage of my 5950X build.

[flashmozzg]

MI200 feels odd. It is dual GPU on board card and it is compared vs single chip A100, that on top of that has some unique properties like ability to split into multiple instances. A100 that is already aging, and is single chip and only having between 1.4x to max 2.4x in aplications better performance on newer process node with still subpar CUDA support is .... questionable.

Also I don't see information about power draw what in such utilization is very important for example 9 out of top10 in Green500 is Nvidia GPU driven.

It's not a dual GPU. It's dual chiplets sort of. Like 1st gen Zen. The connection between the chips is coherent,

[smitty3268]

I am kind of worried about Zen after the latest Intel launch...

Eh, they'll be fine. AMD stock is up more than 15% since ADL launch. There's a reason for that.

It's good that we finally have actual competition around now. Hopefully that means lower prices and more performance for everyone.

[piotrj3]

It's not a dual GPU. It's dual chiplets sort of. Like 1st gen Zen. The connection between the chips is coherent,

that is not what matters, what matters in GPU is if there is one memory controller for 2 chips or 2 memory controllers, eg does 1 chiplet has very fast access to all memory of GPU (way beyond Infinity Fabric, because when IF has to deal with relativly slow RAM, here dealing with HBM in GPU configuration is crazy high bandwitdh far beyond RAM in Ryzen case). And this is serious challenge. If AMD did that, that is very impressive.

[flashmozzg]

that is not what matters, what matters in GPU is if there is one memory controller for 2 chips or 2 memory controllers, eg does 1 chiplet has very fast access to all memory of GPU (way beyond Infinity Fabric, because when IF has to deal with relativly slow RAM, here dealing with HBM in GPU configuration is crazy high bandwitdh far beyond RAM in Ryzen case). And this is serious challenge. If AMD did that, that is very impressive.

AFAIK, they are still no there yet, so moving data between chips has to go through 4 IF 3.0 links, which gives 200GB/second bi-derectional bandwith that is really impressive, and on par for regular GDDR, but just a fraction of the insane HBM2E bandwidth those chips have.