Intel Launches Cooper Lake Xeons CPUs, New Optane Persistent Memory + SSDs

[pal666]

So it appears that Intel is actually doing pretty good with their lithography. Maybe they were behind for a bit, but then overachieved to compensate

i had an impression that they tried to be ahead, but spent several years fixing issues with either performance or yield

[uid0]

https://en.wikichip.org/wiki/File:7nm_densities.svg

Interesting chart, thanks.

So it appears that Intel is actually doing pretty good with their lithography. Maybe they were behind for a bit, but then overachieved to compensate

Density-wise, Intel seems to be at 8.5 nm equivalent node these days, when compared to density of their own previous node: 14 nm / sqrt( 100.76MTr/mm^2 / 37.22MTr/mm^2) = 8.5 nm (14 -> 8.5 -- impressive). TSMC advanced much earlier, but not as far -- both in absolute density terms, and also relative to their own previous node: 10 nm / sqrt(91.2MTr/mm^2 / 51.82MTr/mm^2 ) = 7.5 nm (10 -> 7.5).

Granted, I don't know any details about how transistor density was measured (what kind of transistors/cells? average across a typical chip, or just for blocks of 6T SRAM?), so it is hard to draw conclusions. Also, I imagine Intel are still at a disadvantage if they can't make transistors with gates as narrow as 7 nm, since power consumption would suffer (more gate area -- more capacitance and leakage, so higher both dynamic and static power). I doubt that less die area at smaller node would result in significantly lower chip cost for them, though (quite the opposite for now, maybe).

[vladpetric]

Jees, I cannot take you seriously by making such a fundamental error as stating Global Foundries has a 7nm process, they don't and stopped all development on 7nm in 2018. If you knew what you were talking about you'd be up to speed on that one.

As they say, if you can't blind them with science then baffle them with bullshit.

I was mistaken about that one. Anyway, let me restate - TSMC 7nm only offers a 1.55x improvement over 10nm.

Source: https://en.wikichip.org/wiki/7_nm_lithography_process

Also, on the same page: "In terms of density, N7 is said to deliver 1.6x and 3.3x improvement compared to N10 and N16 respectively. "

The 2x part is a bit history.

Also "Compared to the half-node 10 nm node, N7 is said to provide ~20% speed improvement or ~40% power reduction."

Fundamental issue is that leakage from quantum tunneling only gets worse with smaller feature sizes.

[Slartifartblast]

That used to be the case above 20nm. Not anymore.

Global Foundries 7nm doesn't offer 4x versus Global Foundries 14nm.

Jees, I cannot take you seriously by making such a fundamental error as stating Global Foundries has a 7nm process, they don't and stopped all development on 7nm in 2018. If you knew what you were talking about you'd be up to speed on that one.

As they say, if you can't blind them with science then baffle them with bullshit.

[smitty3268]

Not really ...

10 years ago, yes, one node difference implied considerable power reduction.

These days, static power (leakage due to a transistor being powered on) is much higher and increases considerably with lower feature sizes.

Yes really. Every new manufacturing node that comes out, one of the key marketing numbers that is put out is how much power reduction is possible for the same performance, and it's easy to see that played out in real world products available right now.

For example, TSMC claims:

Compared to its 10nm FinFET process, TSMC's 7nm FinFET features 1.6X logic density, ~20% speed improvement, and ~40% power reduction.

That's a 40% power reduction based on a chip with the same performance as on the older process.

You could argue that Intel's 14nm process is better than TSMC's, but fundamentally the same thing holds true for them.

That's the prime reason they are working so urgently on getting 10nm chips out. It's not about cheaper manufacturing, because they can do 14nm chips cheaper than 10nm. And they aren't hitting the reticle limit in terms of die size. They need the better perf per watt a new process can bring them to compete.

[vladpetric]

Yet density increases only by 1.55x for SRAM cells, for TSMC 10nm->7nm.

You actually said, with respect to nm: "so you should be happy that it represents relative area of memory cell(relative to other nm numbers)". (Obviously, I'm only quoting factual statements that you make in otherwise crap-filled comments).

Well, based on the numbers it absolutely doesn't. Unless you think 1.55x is doubling.

Did you lie, or not?

And I'm not claiming anywhere that Intel isn't behind - far from it. Just that the delta isn't that significant, and it doesn't really make as much of a difference to end users.

To end users, actual performance which includes IPC, performance per watt, and cost matter most (I'm assuming here that overall stability is the same, something which AMD is doing much better now versus 10 years ago).

[pal666]

In transistors, which are not the same thing as functional units. The number of transistors to implement the exact same thing doesn't stay the same between technology nodes

for memory cell it's the exact same number

[pal666]

You claim 4x, I round down from 3.0798 to 3x, and I'm the one lying?

obviously marketing number you see was rounded, they didn't scale it from 14.0000000 to 7.00000000. i didn't expect i have to explain such trivial things

[vladpetric]

from these links tsmc went from 52.51 to 91.2, which is pretty close to doubling, especially if you consider possible amount of rounding between 7 and 8 nm
memory cells have same scheme afaikthat's why intel has uncompetitive prices

i have allergy to bullshit

In transistors, which are not the same thing as functional units. The number of transistors to implement the exact same thing doesn't stay the same between technology nodes

[vladpetric]

You claim 4x, I round down from 3.0798 to 3x, and I'm the one lying?