Intel Launches Cooper Lake Xeons CPUs, New Optane Persistent Memory + SSDs

[pal666]

nanometers are the smallest feature size,

they were many decades ago. features don't shrink with equal rate, so this metric stopped to have any practical meaning and it was changed long ago to realative memory cell area. i.e. with old metric X cell had Y area, so with new metric X/2 cells have Y/4 area, that's all.

And I wasn't talking to you, but rather

spreading bullshit misinformation

[pal666]

That used to be the case above 20nm. Not anymore.

Global Foundries 7nm doesn't offer 4x versus Global Foundries 14nm.

global foundries doesn't have 7nm and will never have

Within the same context, an Intel 14nm SRAM is 0.049µm² (so Intel 14nm is roughly half way in between GF 14nm and GF 7nm).

i already linked you picture with intel 14++ sucking balls compared to competition 10. and i didn't say that equation holds between different vendors. even with equal "smallest feature size" different vendors could have different memory cell areas. but it holds pretty well for one vendor(again you could see nearly double density between 10 and 7 for samsung and tsmc on my link). and when vendor is selling you 6 year old process, he is selling you obsolete shit.

Again, nanometers are the smallest feature size, not the size of a transistor or a memory cell.

again you are still living under a rock.

[vladpetric]

global foundries doesn't have 7nm and will never have
i already linked you picture with intel 14++ sucking balls compared to competition 10. and i didn't say that equation holds between different vendors. even with equal "smallest feature size" different vendors could have different memory cell areas. but it holds pretty well for one vendor(again you could see nearly double density between 10 and 7 for samsung and tsmc on my link). and when vendor is selling you 6 year old process, he is selling you obsolete shit.
again you are still living under a rock.

From these links:

TSMC 10 nm high density SRAM cell: 0.042 µm²
TSCM 7nm high density SRAM cell: 0.027 µm²

That is essentially 1.55x. Do you seriously call that doubling? You're spouting shit and insults at me, and you can't even get what 2x means?

The problem with mega transistors per unit of area is that number of transistors to implement the same thing varies greatly between vendors and technologies as well. Transistors in 10nm technology are a lot shittier than before (i.e., less reliable, more leaky).

Again, I'd ask you to stop.

[pal666]

TSMC 10 nm high density SRAM cell: 0.042 µm²
TSCM 7nm high density SRAM cell: 0.027 µm²

That is essentially 1.55x. Do you seriously call that doubling?

from these links tsmc went from 52.51 to 91.2, which is pretty close to doubling, especially if you consider possible amount of rounding between 7 and 8 nm

The problem with mega transistors per unit of area is that number of transistors to implement the same thing varies greatly between vendors as well.

memory cells have same scheme afaik

Transistors in 10nm technology are a lot shittier than before (i.e., less reliable, more leaky).

that's why intel has uncompetitive prices

Again, I'd ask you to stop.

i have allergy to bullshit

[vladpetric]

You claim 4x, I round down from 3.0798 to 3x, and I'm the one lying?

[vladpetric]

from these links tsmc went from 52.51 to 91.2, which is pretty close to doubling, especially if you consider possible amount of rounding between 7 and 8 nm
memory cells have same scheme afaikthat's why intel has uncompetitive prices

i have allergy to bullshit

In transistors, which are not the same thing as functional units. The number of transistors to implement the exact same thing doesn't stay the same between technology nodes

[pal666]

You claim 4x, I round down from 3.0798 to 3x, and I'm the one lying?

obviously marketing number you see was rounded, they didn't scale it from 14.0000000 to 7.00000000. i didn't expect i have to explain such trivial things

[pal666]

In transistors, which are not the same thing as functional units. The number of transistors to implement the exact same thing doesn't stay the same between technology nodes

for memory cell it's the exact same number

[vladpetric]

Yet density increases only by 1.55x for SRAM cells, for TSMC 10nm->7nm.

You actually said, with respect to nm: "so you should be happy that it represents relative area of memory cell(relative to other nm numbers)". (Obviously, I'm only quoting factual statements that you make in otherwise crap-filled comments).

Well, based on the numbers it absolutely doesn't. Unless you think 1.55x is doubling.

Did you lie, or not?

And I'm not claiming anywhere that Intel isn't behind - far from it. Just that the delta isn't that significant, and it doesn't really make as much of a difference to end users.

To end users, actual performance which includes IPC, performance per watt, and cost matter most (I'm assuming here that overall stability is the same, something which AMD is doing much better now versus 10 years ago).

[smitty3268]

Not really ...

10 years ago, yes, one node difference implied considerable power reduction.

These days, static power (leakage due to a transistor being powered on) is much higher and increases considerably with lower feature sizes.

Yes really. Every new manufacturing node that comes out, one of the key marketing numbers that is put out is how much power reduction is possible for the same performance, and it's easy to see that played out in real world products available right now.

For example, TSMC claims:

Compared to its 10nm FinFET process, TSMC's 7nm FinFET features 1.6X logic density, ~20% speed improvement, and ~40% power reduction.

That's a 40% power reduction based on a chip with the same performance as on the older process.

You could argue that Intel's 14nm process is better than TSMC's, but fundamentally the same thing holds true for them.

That's the prime reason they are working so urgently on getting 10nm chips out. It's not about cheaper manufacturing, because they can do 14nm chips cheaper than 10nm. And they aren't hitting the reticle limit in terms of die size. They need the better perf per watt a new process can bring them to compete.