Intel Launches Cooper Lake Xeons CPUs, New Optane Persistent Memory + SSDs

[Slartifartblast]

That used to be the case above 20nm. Not anymore.

Global Foundries 7nm doesn't offer 4x versus Global Foundries 14nm.

Jees, I cannot take you seriously by making such a fundamental error as stating Global Foundries has a 7nm process, they don't and stopped all development on 7nm in 2018. If you knew what you were talking about you'd be up to speed on that one.

As they say, if you can't blind them with science then baffle them with bullshit.

[vladpetric]

Jees, I cannot take you seriously by making such a fundamental error as stating Global Foundries has a 7nm process, they don't and stopped all development on 7nm in 2018. If you knew what you were talking about you'd be up to speed on that one.

As they say, if you can't blind them with science then baffle them with bullshit.

I was mistaken about that one. Anyway, let me restate - TSMC 7nm only offers a 1.55x improvement over 10nm.

Source: https://en.wikichip.org/wiki/7_nm_lithography_process

Also, on the same page: "In terms of density, N7 is said to deliver 1.6x and 3.3x improvement compared to N10 and N16 respectively. "

The 2x part is a bit history.

Also "Compared to the half-node 10 nm node, N7 is said to provide ~20% speed improvement or ~40% power reduction."

Fundamental issue is that leakage from quantum tunneling only gets worse with smaller feature sizes.

[uid0]

https://en.wikichip.org/wiki/File:7nm_densities.svg

Interesting chart, thanks.

So it appears that Intel is actually doing pretty good with their lithography. Maybe they were behind for a bit, but then overachieved to compensate

Density-wise, Intel seems to be at 8.5 nm equivalent node these days, when compared to density of their own previous node: 14 nm / sqrt( 100.76MTr/mm^2 / 37.22MTr/mm^2) = 8.5 nm (14 -> 8.5 -- impressive). TSMC advanced much earlier, but not as far -- both in absolute density terms, and also relative to their own previous node: 10 nm / sqrt(91.2MTr/mm^2 / 51.82MTr/mm^2 ) = 7.5 nm (10 -> 7.5).

Granted, I don't know any details about how transistor density was measured (what kind of transistors/cells? average across a typical chip, or just for blocks of 6T SRAM?), so it is hard to draw conclusions. Also, I imagine Intel are still at a disadvantage if they can't make transistors with gates as narrow as 7 nm, since power consumption would suffer (more gate area -- more capacitance and leakage, so higher both dynamic and static power). I doubt that less die area at smaller node would result in significantly lower chip cost for them, though (quite the opposite for now, maybe).

[pal666]

So it appears that Intel is actually doing pretty good with their lithography. Maybe they were behind for a bit, but then overachieved to compensate

i had an impression that they tried to be ahead, but spent several years fixing issues with either performance or yield