NVIDIA Announces Volta-based Tesla V100 Accelerator

[phoronix]

Phoronix: NVIDIA Announces Volta-based Tesla V100 Accelerator

NVIDIA CEO Jen-Hsun Huang used the company's GPU Technology Conference to today announce the Volta V100 accelerator for data centers and HPC workloads...

http://www.phoronix.com/scan.php?page=news_item&px=NVIDIA-Volta-V100

[tildearrow]

Umm... 15 TFLOPS of FP63?

[L_A_G]

One minor point I'd like to add to this Michael : TSMC's 12 nm process is just the 4th version of their 16 nm process under a new name. It's somewhat misleadingly named to give the impression that TSMC hasn't fallen behind Intel, GlobalFoundries and Samsung with their 14 nm processes.

[tildearrow]

Still typo... The original blog post mentions 15 TFLOPS of FP32, not FP64...

[andrei_me]

What is AMD doing to compete with nvidia on the Cuda/ AI front? I remember reading that they have a product to port cuda code to OpenCL or something

[bridgman]

What is AMD doing to compete with nvidia on the Cuda/ AI front? I remember reading that they have a product to port cuda code to OpenCL or something

https://streamcomputing.eu/blog/2016...-amd-hardware/

https://github.com/GPUOpen-ProfessionalCompute-Tools/HIP

We are also porting a number of compute frameworks to ROCm ourselves.

[patstew]

One minor point I'd like to add to this Michael : TSMC's 12 nm process is just the 4th version of their 16 nm process under a new name. It's somewhat misleadingly named to give the impression that TSMC hasn't fallen behind Intel, GlobalFoundries and Samsung with their 14 nm processes.

All the companies process nodes have become divorced from any actual physical feature size and driven by marketing. Samsung's 14nm is not the same size as Intel's, and neither is 14/16ths of the size of TSMC's 16nm.

[coder]

As impressive as this chip truly sounds, the timing of its announcement is clearly designed to create FUD for those who'd otherwise consider AMD's Vega. Note that Volta isn't even scheduled to start shipping until Q3. You can bet high demand & production shortages will limit availability and extend stratospheric pricing into Q4 and beyond.

[Peter Fodrek]

>The GV100 GPU has 21.1 billion transistors on a 815 mm2 die. The GV100 is manufactured on a 12nm TSMC

Oh, my God.

A Look at Samsung Foundry’s Business Strategy, Manufacturing Excellence and Advanced Technology Updates

Posted on 04/20/2016

As a result, we have shipped more than half a million wafers for our 14nm FinFET since its introduction with an excellent defect density of sub-0.2 defect/cm2 (Poisson).

http://www.samsungsemiblog.com/foundry/a-look-at-samsung-foundrys-business-strategy-manufacturing-excellence-and-advanced-technology-updates/

28nm process TSMC, of 2011, achieved 0,05 defects pre square cm last year.

http://diit.cz/clanek/samsung-snizil-chybovost-14nm-procesu

Let us assume that TSMC has defect density of 0.2 defect/cm2 for 12 nm process now

0.2 defect/ cm^2 times 8,15 cm^2 (=815 mm^2) =1,63 defects/chip on average.

on the wafer there is defect density lowest in the middle and highest on the egde/ledge, so there is only possibility to have defectless chip in the wafer middle..

[L_A_G]

All the companies process nodes have become divorced from any actual physical feature size and driven by marketing. Samsung's 14nm is not the same size as Intel's, and neither is 14/16ths of the size of TSMC's 16nm.

No, but it's not a new process as the new name is intended to convey.