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The clover implemention in radeonsi is moving pretty slowly right now - main focus has been getting the HSA/ROC stack solid.
We were looking at porting clover to run on top of ROC but had the opportunity to open source our proprietary OpenCL stack instead (after porting it to ROC) so that approach is our current thinking.Test signature
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Originally posted by pal666 View PostimbecileOriginally posted by pal666 View Posti think you are idiot
Originally posted by pal666 View Postit is still modifiable even in rom, it is just harder to modifyOriginally posted by bridgman View Post... which makes no sense, because you could replace the PROM with one that has different contents and you have just updated your firmware in exactly the same way as a microcode flash or filesystem update...Originally posted by wizard69 View PostMind you you a good portion of all hardware is generated from software these days. So why doesn't the FSF demand the code to whatever high level language was used to design the chip?
Originally posted by wizard69 View PostWhich makes no sense at all because code burned into PROM can have bugs also.
Originally posted by bridgman View Post... and in the end this is the ONLY reason for the current belief set regarding HW microcode, with no logical justification whatsoever.
Originally posted by bridgman View PostPurely a matter of convenience, like people criticizing fur but not leather because old ladies are easier to harass than bikers.
An arbitrary decision was made to hack binaries out of packaged distros, and any hardware which still works after that is arbitrarily defined as "good"... leaving us in the situation where microcode stored in a file is bad but EXACTLY THE SAME MICROCODE stored in flash is acceptable.
Stallman and the FSF have done many good things but IMO this is not one of them.
I really have trouble understanding why the HW microcode which runs the GDDR5 link training state machine in the memory controller ABSOLUTELY HAS TO BE OPEN but the rest of the memory controller does not.Originally posted by wizard69 View PostI really think the FSF position is asinine.Originally posted by wizard69 View PostDoes that make sense to anybody?
But you keep on looking for practical reasons and find none, then conclude that the FSF position is asinine.
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Originally posted by bridgman View PostThe clover implemention in radeonsi is moving pretty slowly right now - main focus has been getting the HSA/ROC stack solid.
We were looking at porting clover to run on top of ROC but had the opportunity to open source our proprietary OpenCL stack instead (after porting it to ROC) so that approach is our current thinking.
At least in my case, and probably Jan's, we don't have access to the CL CTS either, so we end up either having to find CL suites that have their own internal tests, or we have to write our own piglit tests before we can attempt to validate the implementation ourselves.
We are within spitting distance of the cppamp driver (from multicoreware) being able to run on Clover, but I haven't been able to find time to finish off the half dozen or so math builtins that need doing. i'm sure there's other similar programs out there that are almost able to work, but missing one or two key built-in functions that we just haven't gotten around to yet.
And at this point, if AMD opens up their full CL driver for me to build/debug, I'm ok with that.... I'll mourn the time I wasted on some software that no longer matters, but I'll get over it (and maybe spend some time going over the AMD code and trying to find some vectorization/optimization opportunities.
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Originally posted by bridgman View PostThe clover implemention in radeonsi is moving pretty slowly right now - main focus has been getting the HSA/ROC stack solid.
We were looking at porting clover to run on top of ROC but had the opportunity to open source our proprietary OpenCL stack instead (after porting it to ROC) so that approach is our current thinking.
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