GNU Binutils 2.42 Brings Support For New Intel CPU Extensions: APX, AVX10.1 & More

[phoronix]

Phoronix: GNU Binutils 2.42 Brings Support For New Intel CPU Extensions: APX, AVX10.1 & More

Nick Clifton with Red Hat announced today the release of GNU Binutils 2.42, the newest feature release to this collection of binary utilities widely relied upon by Linux and Unix-like systems as part of the compiler toolchain...

https://www.phoronix.com/news/GNU-Binutils-2.42

[uid313]

Why did Intel create Intel Advanced Performance Extensions (APX) instead of just using RISC-V or buy a license for ARM? (maybe they already have a license)

Isn't Intel APX a new instruction set architecture that they run side-by-side with x86 in the same core?
Or is Intel APX additional extensions on top of x86 but not a new ISA on its own?

[ehansin]

Why did Intel create Intel Advanced Performance Extensions (APX) instead of just using RISC-V or buy a license for ARM? (maybe they already have a license)

Isn't Intel APX a new instruction set architecture that they run side-by-side with x86 in the same core?
Or is Intel APX additional extensions on top of x86 but not a new ISA on its own?

Take this with a grain of salt, I am certainly not an instruction set expert. But, looked up a Phoronix article (linked below) from last summer, and I reading this as being something added onto the existing instruction set. Kind of like SSE4, though again don't know enough to state anything definitive. More like Intel adding new functionality to their existing instruction set. But minds more versed than me would have to chime in. Adding an ARM or RISC-V core for this wouldn't make sense.

https://www.phoronix.com/news/Intel-APX

[Paradigm Shifter]

Or is Intel APX additional extensions on top of x86 but not a new ISA on its own?

APX goes on top of AMX, etc. It's the ever-moving goalposts of "we need an advantage". We seem to be heading back round the circle into highly optimised ASICs again (from processors which can do everything to a greater or lesser extent) although single-package integration is a thing this time rather than sockets on a board for a math co-processor.

I don't begrudge a company for wanting an edge, but Intel seem to ride a fine line between an edge, anti-competitive practices and anti-monopoly investigations. I found it darkly amusing when AMD were doing so poorly with Bulldozer that people were predicting their doom, as that would immediately mean Intel would face an anti-monopoly probe as the only company to produce x86 hardware (remember, recent improvements in ARM hadn't happened, so it wouldn't be impossible to argue that any company with sole control over x86 was capable of abusing their position...). Intel and AMD both need each other to exist, if only to save legal headaches.

AMD is almost always really late to the party on whatever the latest instruction set is... notice that they just implemented AVX-512 - arguably in a better way than Intel did - and Intel had AMX ready to go with optimisations which AMD can't touch? If Emerald Rapids hadn't missed so many release targets, AMX would probably have already been shipping before AMD got AVX-512 into released silicon. And when AMD get access to AMX, APX will be out (or the next one, even), and so on, forever.

[Anux]

And when AMD get access to AMX, APX will be out (or the next one, even), and so on, forever.

I also think that there is a strategy behind of Intel having an exclusive feature but in reality you see that it needs a few years till those technologies are supported by software and AMD can implement them as soon as there is enough adoption of the technology and therefore has no real disadvantage.

[Paradigm Shifter]

I also think that there is a strategy behind of Intel having an exclusive feature but in reality you see that it needs a few years till those technologies are supported by software and AMD can implement them as soon as there is enough adoption of the technology and therefore has no real disadvantage.

I agree, although it depends. With the current ML/AI enthusiasm, the AMX extensions really help with anything (OpenVINO, OneAPI) optimised for it on a CPU with it (obviously). It was the same for AVX-512. I know I bought Intel servers (or, rather, recommended to the person who makes the decisions that we buy them) because there was an AVX-512 codepath for some of the analysis software we wanted to use, and buying a dozen of the big-boy GPUs was much more expensive than multiple dual-socket Xeon servers with a ton of RAM. But it turned out to be quite a bit more buggy to use the AVX-512 accelerated code, rather than GPUs (also competitiveness with GPU codepath was highly dependent on a lot of factors so user expertise requirement increased which made it harder on newer people) so we still ended up buying a lot of GPUs. It you have people who can write code to support the latest extensions, it's great. If you rely on mainstream commercial software, it can often be a case of they won't expend the time on development of features only for a fraction of their user base.

[colejohnson66]

Why did Intel create Intel Advanced Performance Extensions (APX) instead of just using RISC-V or buy a license for ARM? (maybe they already have a license)

Isn't Intel APX a new instruction set architecture that they run side-by-side with x86 in the same core?
Or is Intel APX additional extensions on top of x86 but not a new ISA on its own?

Two words: backwards compatibility. Unless you control the whole stack like Apple does, switching architectures is out of the question. Look at how long "Windows on ARM" has been a thing (with an x86 emulation layer) and, yet, we're still stuck with x86 machines.

For those who don't know the details:

AVX10 is an augmentation of AVX-512 that allows using the new instructions, but without requiring 512-bit vectors. This goes hand-in-hand with Intel's hybrid architecture approach brought on by Alder Lake. AVX10.1 specifically is just taking the current AVX-512 instruction set and saying "256-bit vector maximum is fine". AVX10.2 is where the real fun changes come.

Intel APX is an extension to the x86-64 architecture that extends the register count from 16 to 32 (matching RISC-V and ARM). It adds new encodings of existing instructions to allow extended functionality (such as suppressing flags), and adds a handful of new instructions.

[ehansin]

I commented up top on stuff that is a littler over my head. Having to read a little between the lines here about stuff I don't totally know. So again, take my original comment with a grain of salt! But I keep reading this comments, trying to pick up bits of pieces here and there.

[mlau]

Isn't Intel APX a new instruction set architecture that they run side-by-side with x86 in the same core?
Or is Intel APX additional extensions on top of x86 but not a new ISA on its own?

APX is a new (longer) encoding for existing x86 instructions to enable 32 registers (instead of 16), a few new conditional move/set instructions, a few new stack operations (to push/pop 2 registers from stack instead of 1).