ARMv8.8-A Support With New MOPS Instructions Ready For GCC 12

[linuxgeex]

Only if your definition of RISC implies that all instructions must be single cycle. However then nothing can ever be called RISC since all ISAs contain a few complex instructions and implementations always have the choice of using multiple cycles for some instructions if that simplifies the overall design. Such complex or multi-cycle instructions don't use microcode because they have been designed to not need it (I guess this is why the 8.8 memcpy is split into 3 separate instructions).

Not a single cycle. Modern CPUs execute multiple instructions per cycle. That has nothing to do with instruction set architecture, and everything to do with microarchitecture.

RISC is meant to do one operation per *instruction*. It should be possible to implement a RISC ISA without microcode. That doesn't mean it can't perform vector instructions, but it does preclude SIMD, and loops encoded as a single instruction.

RISC-V gets around this by implementing instruction stream compression, so that one token can represent multiple instructions. That improves I$ efficiency, and with it, power/area and effective bus bandwidth without surrendering what it means to be RISC. ARM can do the same, and probably will. For application processors it makes a lot more sense than Thumb as a way to increase code density.

[PerformanceExpert]

Not a single cycle. Modern CPUs execute multiple instructions per cycle. That has nothing to do with instruction set architecture, and everything to do with microarchitecture.

RISC is meant to do one operation per *instruction*. It should be possible to implement a RISC ISA without microcode. That doesn't mean it can't perform vector instructions, but it does preclude SIMD, and loops encoded as a single instruction.

Again that is a dogmatic view since all RISCs, including the early designs, have instructions that did more than one operation without needing microcode - for example compare and branch, multiply and add, load/store with writeback, SIMD. It makes sense to add powerful instructions when they are easy to implement - the extreme of a purist RISC is as bad as making a CISC.

RISC-V gets around this by implementing instruction stream compression, so that one token can represent multiple instructions. That improves I$ efficiency, and with it, power/area and effective bus bandwidth without surrendering what it means to be RISC. ARM can do the same, and probably will. For application processors it makes a lot more sense than Thumb as a way to increase code density.

Thumb has used a mix of 16-bit and 32-bit instructions for code density for like 2 decades. However code density is mostly relevant for tiny microcontrollers, not for 2021 application processors with huge caches! And it's not like the code density gains are significant compared to a dense fixed-length encoding like AArch64. Worse, variable length encodings are bad for wide, high-performance designs.