Originally posted by oiaohm
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You can't have it both ways.
Previously you said that a RISC CPU can implement division in 1 clock cycle and other clueless bullshit which is literally impossible in physics. Now you say that a division is multi-uop and macro op and goes to multiple execution units despite only having register operands. Which makes it a CISC instruction.
So which one the fuck is it?
Originally posted by oiaohm
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