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Radeon HD 7000 Series Will Bring New 3D Driver

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  • bridgman
    replied
    For GCN and up, this code + LLVM will more-or-less replace the shader compiler in r600g; at least that's our current thinking. The compiler will accept either TGSI or LLVM IR depending on whether the graphics or compute state tracker is running.

    For graphics, the path will be :

    [GLSL] >> (GLSL compiler) >> [glsl ir] >> (GLSL IR to TGSI converter) >> [tgsi] >> (new tgsi to llvm code) >> [llvm ir] >> (new llvm to ISA code) >> [gpu instructions]

    ..while for compute the path will be :

    [OpenCL C99] >> (clover using clang/llvm) >> [llvm ir] >> (new llvm to ISA code) >> [gpu instructions].

    Something like that anyways. There are a couple of points in the stack where LLVM runs some optimizing passes on the IR but I don't remember offhand where they are and need to get back to chopping firewood so am not looking at the code right now

    square brackets for [data], parentheses for (processing)
    Last edited by bridgman; 11 December 2011, 07:00 PM.

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  • Drago
    replied
    As mud, yes
    Now to summarize...the code Tom pushed is part of a compiler stack for OpenCL/compute. It has <=CHIP_CAYMAN for now, with CHIP_GCN landing after some time.
    This will not replace any part of the Graphics pipeline. This code will integrate in mesa and is the back-end with front-end clover state tracker.
    What about Graphics for GCN, e.g. graphics shader compiler?

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  • bridgman
    replied
    I thought it would have been obvious from the diagram



    Seriously, I understand it's not obvious at all. If you look at the center-left of the diagram you'll see a little "you are here" guy with a few lines going off to the right and upper right. The line going off to the right is the common compiler work for OpenCL and GCN - at the end of that line there's another line going up into OpenCL work and a line going down into GCN work, with the internal name of the GPU family scribbled over in black. Going from memory, the line going up to OpenCL should be making the compiler code work with clover while the line going down to REDACTED should be adding the HW-specific ISA bits.

    So... the compiler work is common to GCN and compute/OpenCL support, but the reason for releasing it now was more for people working on compute and that's what most of the mailing list comments talked about. We are not pushing out the GCN-specific HW programming bits yet but we are trying to push out the stack that GCN will use.

    In most cases we are using Cayman for testing the stack changes since it is architecturally closest to GCN, however in the specific case of the compiler we want to support everything from Evergreen up since Evergreen is where the main HW features required for efficient OpenCL work arrived.

    Clear as mud ?
    Last edited by bridgman; 11 December 2011, 06:23 PM.

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  • Drago
    replied
    Well, I thought this thread is for HD 7000 3D driver, not for openCL back-end. If it is not the case, then my bad and sorry for that.
    There is no references in the this code for any chip >CHIP_CAYMAN.

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  • agd5f
    replied
    Originally posted by Drago View Post
    Where....?

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  • Drago
    replied
    Originally posted by bridgman View Post
    ... and compiler code is now out (minus the GCN-specific bits, of course)
    Where....?

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  • bridgman
    replied
    Originally posted by bridgman View Post
    Multiple ring support was pushed out a month or two ago, while the memory mgmt and compiler code are getting fairly close...
    ... and compiler code is now out (minus the GCN-specific bits, of course)

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  • blackshard
    replied
    Originally posted by Smask View Post
    You mean the (not) new mobility parts?
    I meant those installed in the low power APUs:



    As far as I understand, radeon 7200 and 7300 are just a rebranding.

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  • Smask
    replied
    Originally posted by blackshard View Post
    Well actually you were right, there will be some VLIW5 parts too (Brazos 2.0).
    You mean the (not) new mobility parts?

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  • bridgman
    replied
    Originally posted by airlied View Post
    ... and as such the fastest way to write one is to duplicate an existing one, remove stuff that doesn't apply and fill in the blanks.
    The underlined part covers another important point -- the GCN architecture is different from current hardware but not *totally* different. For the parts of the hardware that don't change (or don't change much) it's a lot easier to start with working code for the previous generation than to write everything from scratch.
    Last edited by bridgman; 09 December 2011, 03:55 PM.

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