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  • atombios ports

    Hi,
    I'm into the atombios and I wonder about ports.

    "AMD(ATI) port" is direct or indirect MMIO. Is modern atombios bytecode (from evergreen) still use indirect access? Because to access the PLLs and MC there are opcode argument types which would obsolete the indirect MMIO, wouldn't they?

    The current interpreter does ignore the "PCI port" and "SYSIO port", is this safe for a OS driver to ignore them?

  • #2
    Originally posted by sylware View Post
    Hi,
    I'm into the atombios and I wonder about ports.

    "AMD(ATI) port" is direct or indirect MMIO. Is modern atombios bytecode (from evergreen) still use indirect access? Because to access the PLLs and MC there are opcode argument types which would obsolete the indirect MMIO, wouldn't they?
    Yes. indirect is still used. It's actually the other way around. The PLL and MC arguments were replaced with the IIO stuff a while ago since it covers any indirect space including the PLL and MC spaces. Newer cards do not even have indirect PLL or MC spaces anymore, but they do have other new indirect spaces.

    Originally posted by sylware View Post
    The current interpreter does ignore the "PCI port" and "SYSIO port", is this safe for a OS driver to ignore them?
    yes.

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    • #3
      Then, only AMD(ATI) port:
      Direct MMIO and indirect MMIO for PLL/MC (and more...). PLL and MC args are obsolete.

      The indirect io data table is then mandatory to set up.

      Oh! And is this normal that when writing a value in register index 0, using direct MMIO, the value fetch by the interpreter to write seems to be a dword index and not a byte index (namely it's multliplied by 4)?

      Thx!

      Comment


      • #4
        Originally posted by sylware View Post
        Then, only AMD(ATI) port:
        Direct MMIO and indirect MMIO for PLL/MC (and more...). PLL and MC args are obsolete.
        Only for newer asics. The older ones still use the PLL and MC args.

        Originally posted by sylware View Post
        The indirect io data table is then mandatory to set up.
        Yes.

        Originally posted by sylware View Post
        Oh! And is this normal that when writing a value in register index 0, using direct MMIO, the value fetch by the interpreter to write seems to be a dword index and not a byte index (namely it's multliplied by 4)?
        All registers accessed via ATI port use dword offsets.

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        • #5
          thx a million

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