AMD Announces Embedded+ Architecture For Ryzen Paired With Xilinx IP

[maximus8086]

How much will it cost?

How much will it cost an enduser SBC with them?

Whst are the features and capabilities of the FPGA part?

I would love a cheaper and really powerful replacement of DE10 Nano, useful for Mister. They can deal up to N64, PSX and Saturn with it. With a lot more poweful hardware, maybe even Dreamcast and use SoC hardware to do tricks (ethernet emulation, faster load times, emulate more ram and hack games, 4K GPU rendering, etc).

Unfortunately Intel/Altera doesn't really have any affordable midrange products that would be useful as successors to this. Probably the next most reasonable step would be something like AMD/Xilinx's Kria KR260 Robotics Starter Kit.

The Versal device used in this Embedded+ system is a high end commercial grade part; as other users said, it's well outside an individual's price range.

[pong]

I guess it depends on what you mean by SOC.
You can put some pretty capable RISC-V processors into not that much PL area for the processor itself,
small few kLE for a basic MCU, several tens of kLE and way up over that figure for more of a basic application processor.
If you're trying to compete with ARM-A multi-cores at GHz speeds in PL then that's generally a losing proposition wrt.
speed and cost per MIPS though it may be possible on a relatively big FPGA.

But on-FPGA fast RAM has always been limiting in size for DRAM-alternative or even cache / buffer faster than DRAM
or having independent latency / port.

Though integrated with an APU or whatever they're calling this hybrid device I would be pretty optimistic that it
can talk to system RAM fast (one would hope / think) through a bridge and that maybe it'd even be able to talk to
system cache or some such on chip memory subset partitioned away from the cache for FPGA use fast.

The FPGA is most likely just for I/O. it may not be big enough to implement an SoC.

This is very clearly aimed at industrial partners for whom price does not even remotely matter.

[pong]

KV260 even lower cost though the SOM is significantly limited if you're building a full featured baseboard to use the SOM and
the KR260 has better carrier board I/Os for its envisioned purposes vs the CV oriented KV. Different interfaces for different use cases
(cameras vs. ethernet etc.) but both good basic FPGA-SOC kits.

Unfortunately Intel/Altera doesn't really have any affordable midrange products that would be useful as successors to this. Probably the next most reasonable step would be something like AMD/Xilinx's Kria KR260 Robotics Starter Kit.

The Versal device used in this Embedded+ system is a high end commercial grade part; as other users said, it's well outside an individual's price range.

[Developer12]

I guess it depends on what you mean by SOC.
You can put some pretty capable RISC-V processors into not that much PL area for the processor itself,
small few kLE for a basic MCU, several tens of kLE and way up over that figure for more of a basic application processor.
If you're trying to compete with ARM-A multi-cores at GHz speeds in PL then that's generally a losing proposition wrt.
speed and cost per MIPS though it may be possible on a relatively big FPGA.

But on-FPGA fast RAM has always been limiting in size for DRAM-alternative or even cache / buffer faster than DRAM
or having independent latency / port.

Though integrated with an APU or whatever they're calling this hybrid device I would be pretty optimistic that it
can talk to system RAM fast (one would hope / think) through a bridge and that maybe it'd even be able to talk to
system cache or some such on chip memory subset partitioned away from the cache for FPGA use fast.

It's attached over PCIe. This is basically a PCIe-attached FPGA card, but on the same package as the CPU.

[timofonic]

The FPGA is most likely just for I/O. it may not be big enough to implement an SoC.

This is very clearly aimed at industrial partners for whom price does not even remotely matter.

Damn. I hope someday AMD makes really useful and powerful and affordable products from Xilinx IP portfolio, not this stupid overpriced stuff.

[Developer12]

Damn. I hope someday AMD makes really useful and powerful and affordable products from Xilinx IP portfolio, not this stupid overpriced stuff.

The xilinx portfolo are be definition out of the price range of the average consumer. It's why you don't see a lot of FPGAs in consumer equipment except that which that costs $$$$$.

[pong]

Well I guess that depends on what you mean really useful and powerful and affordable means.
You can compare the Raspberry PI to the KV260/KR260 and on the one hand say that the xilinx ones cost 6-8x as much
as a RPI (very approximate figures from memory and they're basically "competing" with the Nvidia Jetsons etc. to some extent for some part of the market) but OTOH they're a LOT more customizable than the RPI where you've got ~all the processing power goodness wrt. the ARM AP-SOC but then
you've got the PL and I/O capabilities that are several orders of magnitude better than the handful of GPIO/SPI/I2C/UART/camera/display/ethernet interfaces on a RPI since they have all that and more and still O(100k) LEs of PL you can do whatever with, GB/s transceivers, etc.

Granted it's not like I'm going to be replacing a 4090 GPU or EPYC CPU with a Virtex-something for the same / better cost for more performance anytime this year but they're not intended for that kind of commodity use, they're intended for stuff like you're building a MRI and you've got hundreds of channels of things needing real time control and hundreds of MHz of data acquisition you need to do and it's all "custom".

Damn. I hope someday AMD makes really useful and powerful and affordable products from Xilinx IP portfolio, not this stupid overpriced stuff.

[pong]

Thanks for the information. I hadn't looked at the architecture to see what kinds of PL / PS bridges they implemented for these.
It makes sense from a device driver perspective since it just fits into the ordinary PC PCIE peripheral mold from the OS side, though
that also likely means it doesn't have huge bandwidth and not so much in the way of memory cache / ram access / sharing autonomy
as might've been the case had they integrated it as something more like a "coprocessor" though coprocessors have been "out of style" for
a long time now so that's understandable.

I guess CXL would be the more "over PCIE electrically" but more closely integrated in the system's compute / memory architecture middle-ground these days.

AFAIK there's "a lot" of PCIE linked custom / "high performance" NICs that end up talking to FPGAs via PCIE for protocol offload / DMA etc. well at least
before there got to be quite so many standard chipsets for that sort of thing at NNN Gb/s speeds.

It's attached over PCIe. This is basically a PCIe-attached FPGA card, but on the same package as the CPU.

[timofonic]

The xilinx portfolo are be definition out of the price range of the average consumer. It's why you don't see a lot of FPGAs in consumer equipment except that which that costs $$$$$.

Why are they so insanely expensive? Are they made of pure gold?

[Developer12]

Why are they so insanely expensive? Are they made of pure gold?

An FPGA is always going to be an order of magnitude more expensive than the thing you use it to build, if it had been instead implemented on an ASIC.

An FPGA that someone has used to implement, say, a CPU isn't a CPU. It's a chip with a huge number of logic units that have been configured and connected such that each logic unit can emulate a couple of gates in the CPU design. All those logic units are far larger than the couple of gates they emulate, due to needing a ton of circuitry for being configurable. There's also a ton of area lost in routing and crossbar switching, since all these units need to be able to be connected together in arbitrary ways. Most of the area of the chip is actually just huge amounts of routing infrastructure.

AND THEN there's the fact that all of this extra length and complexity inherently means there's going to be a speed penalty, so they do a ton of work to try to minimize that. Easiest way to do that is to build the FPGA on a much, much fancier manufacturing process than the chip you want to emulate would be, which adds a shitload of cost.