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AMD-Pensando Elba SoC & A Massive RISC-V 64-Core Chip Supported In Linux 6.7

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  • AMD-Pensando Elba SoC & A Massive RISC-V 64-Core Chip Supported In Linux 6.7

    Phoronix: AMD-Pensando Elba SoC & A Massive RISC-V 64-Core Chip Supported In Linux 6.7

    There is some interesting new Arm and RISC-V SoC support to be found in the in-development Linux 6.7 kernel...

    Phoronix, Linux Hardware Reviews, Linux hardware benchmarks, Linux server benchmarks, Linux benchmarking, Desktop Linux, Linux performance, Open Source graphics, Linux How To, Ubuntu benchmarks, Ubuntu hardware, Phoronix Test Suite

  • #2
    I can't wait for the ecosystem to mature enough for me to build my first RISC-V Linux Workstation.

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    • #3
      Originally posted by aviallon View Post
      I can't wait for the ecosystem to mature enough for me to build my first RISC-V Linux Workstation.
      Same!

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      • #4
        Originally posted by aviallon View Post
        I can't wait for the ecosystem to mature enough for me to build my first RISC-V Linux Workstation.
        Originally posted by M.Bahr View Post

        Same!
        Related: The official Debian RISC-V build is already at around 96% of all packages.



        Relevant with Debian being the largest distribution in several senses, including size of software package library, development community and distributions based on it.

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        • #5
          Would there be any performance benefits from cutting out the CPU scheduler completely? In a system with 64 cores, assign one core for interrupts and have the rest perform one task until it is complete, and emit error if more than 63 tasks are trying to run concurrently?

          It would seem the CPU cycles for the scheduler would free up performance, and cache locality would be 100% also would improve performance.
          Last edited by varikonniemi; 04 November 2023, 07:55 AM.

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          • #6
            Originally posted by varikonniemi View Post
            Would there be any performance benefits from cutting out the CPU scheduler completely? In a system with 64 cores, assign one core for interrupts and have the rest perform one task until it is complete, and emit error if more than 63 tasks are trying to run concurrently?

            It would seem the CPU cycles for the scheduler would free up performance, and cache locality would be 100% also would improve performance.
            Bit late, but... don't they do such things in HPC? I don't think it'd make much sense on a desktop for a variety of reasons (63 tasks is not enough, many tasks are long-running but idle much of the time, ...) but this chip is quite obviously not intended for desktops anyway since lots of slow cores is not what you want there.

            In any case, really looking forward to seeing some benchmark numbers on this thing. And, hopefully, a deep dive on chips&cheese

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