Intel Xeon Max Performance Delivers A Powerful Combination With AMX + HBM2e

[DavidBrown]

As long as the traces don't double-back on themselves, then we're still talking about no worse than a Manhattan distance which, in the worst case, should be just sqrt(2) as long as the direct path.

Actually, traces can be a good deal longer than that. Sometimes you need longer traces to go around obstacles or because of limited routing space, though the pin layout on chips like these are designed to minimise the risk of that.

But the main issue is, as jrdoane said, controlling skew. Your data lines all come in groups of between 4 and perhaps 32 data signals. (Different bus types and memory types use different grouping.) Each group has a clock (invariably differential for high-speed buses), and perhaps also strobes, enables, or other control lines. These are all synchronous to the clock, and need to be sampled by the receiving end at the same clock edge. In order to get the best possible signal, you need the lines to have the same length (or, more precisely, the same signal propagation time - but unless you are doing something really weird with the layout and characteristic impedances, that will mean the same length). Then ringing, rise/fall slopes, cross-talk, etc., will be at a minimum at the same time for all signals in the group, and that is your sample point.

This means that signals that are physically closer might need trombone routing (wiggling back and forth) to make them longer, so that all signals in the group have closely matched lengths. It does not matter much if the signals are a bit longer than optimal - length matching is more important to reduce signal skew.

Again, this matters more when the signals are faster.