RISC-V Summit 2021 - High Performance Processors, Other Interesting Talks

[phoronix]

Phoronix: RISC-V Summit 2021 - High Performance Processors, Other Interesting Talks

Taking place in San Francisco from Monday through yesterday evening was the RISC-V Summit for discussions around this dominant open-source processor ISA. For those that were did not make it to the event, many of the slide decks are available...

https://www.phoronix.com/scan.php?page=news_item&px=RISC-V-Summit-2021

[tuxd3v]

Michael well you read my mind
I passed all night patching debian stable mesa, to have vaaapi acceleration, and building the stack, 3 times, and I managed to get vaapi acceleration, but not with good quality..
It will be relegated to another night, were I would be "in another mission.."

I liked specially the runing debian in Syntacore scr7:

https://static.sched.com/hosted_files/riscvsummit2021/36/Demo%20Debian%20Linux%20at%20octacore%20SCR7-based%20SDK.pdf

Ho, and in the keynote from the Chief Commercial Office of Syntacore:

https://static.sched.com/hosted_files/riscvsummit2021/14/syntacore_riscv_summit.pdf

here he announces the scr6( comparable to cortex 7m till 1.5Ghz )
he also drop some notes about the next design..
yeah, it will be Quad issue, server entry level performance, hypervisor and stuff...

I believe SiFive is maybe 6 months on front of Syntacore,
Because SiFive already announced its cortexA77 competitor..and Syntacore will release its one in 2022

There are there also there very interesting ones from WesternDigital, and also Andes.. very nice stuff going on this days.

[skeevy420]

phoronix

For those that were did not make it to the event

It's not really a typo but I noticed it on the main page.

[Developer12]

"open source"

Their mailing lists are closed. Their working groups are closed. Their process for proposing extensions is closed. All of the above also require NDAs.

And then on top of that the chip designs and datasheets from most manufacturers still require NDAs, if they're available at all. Nothing's changed there.

I really don't see any of the "openness" here that other people seem to see, beyond "you won't be sued for patent infringement by ARM"

[tuxd3v]

"open source"
Their mailing lists are closed. Their working groups are closed. Their process for proposing extensions is closed. All of the above also require NDAs.

And then on top of that the chip designs and datasheets from most manufacturers still require NDAs, if they're available at all. Nothing's changed there.

I really don't see any of the "openness" here that other people seem to see, beyond "you won't be sued for patent infringement by ARM"

At least the ISA is open to anyone..
There are opensource designs, picorv32, or syntacore scr1.. and maybe others for sure..
However, the level of performance for the opensource parts cannot compete with ARM, you need the full IP( which is closed source ), to get it to surpass the arm cortex m3..

Yes to access that technology for testing, and to feel at home with it.. yes you need to sign NDAs..but you will need to sign them anywhere you will try to get access to the hardware..
But yeah the proposal of extensions, introductions, etc is made in some closed format...only members of RiscV International will access..
This companies also need to survive, you need to consider that too.

But the Idea of having a open ISA, just think about it, is tremendous..it will allow companies to develop their own full cpus stacks, optimize them without having to worry with Legal penalizations,...because they are using a open ISA..its huge.

[Developer12]

At least the ISA is open to anyone..
...
But the Idea of having a open ISA, just think about it, is tremendous..it will allow companies to develop their own full cpus stacks, optimize them without having to worry with Legal penalizations,...because they are using a open ISA..its huge.

I think we agree in the ways that this ISA is open. You won't get sued for using it, although nobody can suggest extensions or access powerful chips without signing NDAs.

However, "not getting sued for using it" isn't a particularly unique property. SPARC, MIPS, POWER, OpenRISC, and many others also fall into this category. Compared with RISC-V, many of these have FAR more mature software ecosystems, or did at one point. All four have mature linux kernel and toolchain support, and at least 3/4 have had official package support for a number of years in a variety of distros.

The only reason I think companies are hopping on the RISC-V bandwagon is because it's "new" and so they've been infected with the hype bug while also salivating at the prospect of not paying ARM fees. For them, openness isn't a requirement.

[PerformanceExpert]

Michael well you read my mind
Ho, and in the keynote from the Chief Commercial Office of Syntacore:

https://static.sched.com/hosted_files/riscvsummit2021/14/syntacore_riscv_summit.pdf

here he announces the scr6( comparable to cortex 7m till 1.5Ghz )
he also drop some notes about the next design..
yeah, it will be Quad issue, server entry level performance, hypervisor and stuff...

That link talks about the 2-way SRC7 core which barely outperforms a Pi 3B... That's bad performance for an in-order - however if it is really out-of-order as claimed then that's absolutely terrible performance.

[brucehoult]

"open source"

Their mailing lists are closed. Their working groups are closed. Their process for proposing extensions is closed. All of the above also require NDAs.

There are no NDAs for any of that. The mailing lists are public. All you have to do to get access to working groups to propose extensions or modifications to in-progress extensions is to sign a zero cost (for an individual) membership agreement.

I'm an individual member of RISC-V International -- I don't work for any RISC-V company -- and a number of my proposals for instructions or modifications to instructions or clarifications to the specs have been accepted (and now ratified). And some have not. That's the democratic process.

And then on top of that the chip designs and datasheets from most manufacturers still require NDAs, if they're available at all. Nothing's changed there.

That's nothing to do with RISC-V International. They are only the keepers of the spec.

There are cores and chips from commercial companies and of course they want you to do the normal commercial things.

But there are also a number of open-source and license-free cores and entire SoCs (more at the microcontroller level).

Alibaba recently open-sourced the entire RTL for four cores at various performance levels -- the top one at roughly ARM A72/A73 level -- under Apache 2.0 license:

https://github.com/T-head-Semi/openc910

[brucehoult]

That link talks about the 2-way SRC7 core which barely outperforms a Pi 3B... That's bad performance for an in-order - however if it is really out-of-order as claimed then that's absolutely terrible performance.

That is absolutely standard and normal performance for an in-order such as ... the ARM A53, which is still shipping in many phones and tablets as well of course as the wildly popular Pi 3.

There have recently been some higher-performance dual-issue in-order enabled by adding a 2nd "late" ALU pipe stage. Examples of this include the SiFive U74, the Western Digital SWeRV (both RISC-V) and the ARM A55.

ARM recently announced the 3-wide in-order Cortex A510. That's interesting, but it's not part of the landscape yet.

[juarezr]

The only reason I think companies are hopping on the RISC-V bandwagon is because it's "new" and so they've been infected with the hype bug while also salivating at the prospect of not paying ARM fees. For them, openness isn't a requirement.

Saying that's because is new maybe would sound a bit exaggerated.

RISC-V is extremely well designed:

• It's stupidly simple: 50+ instructions for a simple processor.
• It's composable: combine the instruction sets you need: base + float + double + compressed + vector + packed simd + bitwise + whatever
• Vector instructions are not progressive hacks like SSEs, AVXs (it's configurable and flexible)
• It doesn't impose any absurd new restrictions on architecture (like Itanic)
• It has just a few layouts for instructions ( 6 for the base set ) with registers, opcodes, flags always in the same bit position making really simpler things like instruction decoding, prefetching, loop/jump prediction

Of course, there are pretty good ISAs besides RISC-V. It's undeniable.

However, RISC-V technical merits definitively played a major role in the explosive growth inside all of the major players, including ARM (nVidia built a microcontroller for it's cards).