Originally posted by coder
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- the big priority for G3 is the chiplet design (with getting SVE and v9 support into tools and OS a second-level concern)
- and V1 gave them a six month time advantage over N2.
Presumably, depending on what they conclude about the chiplet design, they'll either respin right away (using N2, new product in 6..9 months?) or wait 12..18 months and use N3.
Two interesting things about the chiplet design suggest themselves:
(a) the memory controllers are on separate chiplets. Given the extra area, are these "integrated" designs like Apple is using. The Apple design has the SLC as, essentially, a cache in front of the DRAM (as opposed to a cache on top of the L2's) with advantages in both how the cache interacts with the memory controller, and in how coherence is handled. Given extra chiplet area, you can replicate the Apple design with something serious like a 32MiB cache on each chiplet.
(b) what's the win in using chiplets this way? The obvious idea that suggests itself is
- CPU on 5nm (expensive, constrained, but highest performance/watt)
- mem controller (+LLC?) on 7nm (cheaper, not much of a downside if most of your area is SRAM anyway)
- PCIe IO on 16nm (large analog footprint)
?
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