AMD Ryzen 7 5800X Linux Performance

[oiaohm]

The 4-core/etc parts MAY be defective CCXs, but they may also be fully-functional CCXs with cores lasered off (or disabled by other means). It's called product segmentation, and you don't understand it at all. (Though it's counter-intuitive, so I don't blame you for that). I'll see if i can remedy that...

This is you have missed something how the AMD market is segmented and the demards.

Think of it like this: even if AMD was getting perfect yields, as soon as they have ANY "surplus" dies - not just defective ones - it would STILL be worth castrating some 5600s to "3400"s, because it's still a double win: they make less profit than they would if the part was sold AS a 5600, but it ISN'T being sold as that, because that's what the definition of "surplus" is. But it's still *a* profit (and technically, a larger one since the profit on an unsold unit is 0), and it *denies Intel that sale*.

Question is where is AMD going to have surplus dies and the answer is does not fit your idea. You have looked down the stack you have failed to look up. The released EPIC cpus are all Zen 2 at this stage. EPIC Zen 3 release will be needing dies. To be correct 8 and 6 core dies.

This is a simple over look Ryzen 5 5600, AMD Ryzen 9 5900X and not released yet EPIC Zen 3 cpu all need 6 core chiplets. The 8 core chiplets will also be going out though three different doors at least. Threadripper solutions are another door. 8 and 6 core chiplets in the AMD model has 3 to 4 outlets. So AMD can sell as many of them as they can make in the 3-8 core chiplets. You have missed that a Ryzen 5 5600 is a downgrade profit from the same chiplet sold in AMD Ryzen 9 5900X and will be downgraded profit to the same chiplet sold in a Threadripper or Epic part.

4 core chiplets those have at best 2 outlet in the 3400 series but in the Zen3 series only 1 at best. Remember you still have customers in servers buying Zen 1 and Zen 2 based chips so you are going to have the failed yield from them to put into 4 core chip market.

Lets say AMD does release a Ryzen 3 5xxx is this going to hinder AMD selling the failed Zen2 parts that come the "3400"s yes it is.

There is very little benefit to AMD to ruin good chiplets as they need as many good Zen3 chiplets as they can get.

You have missed that AMD have delayed the Epic and Threadripper releases using Zen3 because there is not enough Zen3 6 and 8 core chiplets to go round then you suggest the idea of lets intentionally ruin some.

This is why I suspect we might be waiting until Zen 4 before we see a new Ryzen 3 as it just does not make sense with AMD demards to make a Ryzen 3 for Zen3 at the moment unless there happens to be enough chips failed with like 5 working cores or less. With yield increases when you stay at a nm level there may not be the failed production or at least not enough to justify disrupting the "3400"s sales..

[arQon]

s/3400/5400/ - sorry about that.

As for the rest, well, I guess we'll see how things turn out over the next year or so. I haven't "missed" any of the things you imagine, and it's clear you still don't understand how this business actually works, and are still hung up on the *absolutely incorrect* notion that a 5400 part can only come from a stockpile of dies "with like 5 working cores or less".

Obviously it would be stupid to make "5400" parts NOW, as you say, but "now" is just a few weeks after the Zen3 launch. Once that initial demand is over, the situation becomes very different. Zen4 may show up before the 5400, or it may not. I strongly doubt it, but at this stage it's all guesswork. Like I say, we'll see.

[oiaohm]

As for the rest, well, I guess we'll see how things turn out over the next year or so. I haven't "missed" any of the things you imagine, and it's clear you still don't understand how this business actually works, and are still hung up on the *absolutely incorrect* notion that a 5400 part can only come from a stockpile of dies "with like 5 working cores or less".

This is because you have missed a few thing.

Obviously it would be stupid to make "5400" parts NOW, as you say, but "now" is just a few weeks after the Zen3 launch. Once that initial demand is over, the situation becomes very different. Zen4 may show up before the 5400, or it may not. I strongly doubt it, but at this stage it's all guesswork. Like I say, we'll see.

What you are missing is when the initial demand dies down for the Ryzen 5 5600 and AMD Ryzen 9 5900X its then time to release either the threadripper or epic that uses the 6 core dies. So the 6 cores chiplets are going to remain at initial demard level for quite some time.

Ryzen 4000 chips remember these have only been released OEM only because AMD could not get enough FAB production at TSMC to do a global release at this stage.

Zen 3 chips are in a very different fab access position to when Zen 2 was released. When Zen 2 was released TSMC had spare capacity AMD could ask for. By the time of Zen 4000 that spare capacity is not there so you get what you booked on the FAB nothing more for quite some time.

Using a lazer to downgrade a product to put in in the market only makes sense in 2 cases.
1) you are sure to get more supply to replace what you have downgraded. AMD with the pressure on TSMC from other parties cannot be sure of this. Apple has not been able to order all the M1 they want from TSMC because supply in 5nm is getting capped out as well.
2) you don't have suitable competitive products in that segment. Zen2 parts are suitable competitive at this stage in the Ryzen 3 segment.

The reality it may be stupid to make 5400 chips at all because that could undermine means to make the EPIC and Threadripper Zen 3 chips before Zen 4 release.

My limitation of with 5 working cores or less limitation for making the 5400 is allowing for how restricted AMD chiplet supply is and the need to make newer EPIC and Threadripper parts to keep their market position in those markets as well.

Not releasing a 5400 chip is not going to majorially damage AMD position in the desktop market. Not releasing newer threadripper or epic chips could put therm at risk. Remember different parties are entering the epic market with arm based chips so intel is not their only threat in that market. This is the problem you are overlooking AMD need to release the EPIC in Zen3 at least sometime in the next 12 they have to have the supply of chiplets to-do that they cannot afford to destroy that supply to make 5400 chips. If there are enough failed chips that are not suitable for EPIC or threadripper then we could see 5400 chip sooner.

My point here you are overlooking the doors 6 core chiplets are need for and the fact AMD is not in location to ignore the EPIC side forever. So there is going to be at least two initial demand windows with need to build up supply before putting product on market with the EPIC. Horrible as it sounds you could be looking at 6 months before product launch the pressure on chiplet supply with AMD in current envornment,


arQon think order of importance where does the 5400 sit compared to the EPIC and Thread-ripper Zen 3 for AMD market control. While there are future chips needing the 6 core chiplets with TSMC FAB restricted supply lazering them down is not a practical move.

AMD chiplet model does make supply chips a more complex model. With intel chips the idea after the initial release sorts out they will cripple chips to expand market coverage makes sense. The AMD chiplet model means we have not seen all the initial releases demands for chips that use the 6 core chiplet yet and AMD at moment needs to be stock piling 6 and 8 core chiplets for the EPIC and Threadripper releases. Yes we are 2 weeks after only first of the 3 initial releases using 6 core chiplets. With amd general spacing between releases we could be looking at the demand for 6 and 8 core chiplets in Zen 3 only dropping off once Zen 4 releases.

I would say with AMD set of pressures if a Ryzen 3 appears in Zen 3 its more likely to be a APU from a non chiplet production run.

[arQon]

The reality it may be stupid to make 5400 chips at all because that could undermine means to make the EPIC and Threadripper Zen 3 chips before Zen 4 release.

Except we've already established that isn't the case in this scenario.

While this discussion has had its highlights, at this point you're just being wilfully obtuse, so we should stop here. Hopefully AMD will have enough capacity next year for coverage either way.

[artivision]

I'm not sure what you mean by "prediction" - I don't think you are referring to a branch predictor, are you ? That's the only "prediction" I can think of in a modern processor other than cache and memory prefetchers.



I don't think I understand your point. When you say "my architecture" are you talking about the use of hardware dependency analysis at runtime, ie every OoO processor on the market except for Denver, Itanium and other VLIW designs ?

All OoO processors keep their in-flight instructions in a reorder buffer (I think ARM sometimes calls it a commit queue) in program order then instructions execute out of order as soon as their dependencies are available.

What you describe about "some apps will use 3 and some 7" is exactly how all OoO processors operate today... the number of instructions executed in parallel is a function of the ILP that can be extracted from the code within the instruction window. On average a modern CPU executes 2-3 instructions per clock but can peak at 6-8.

BTW something interesting just occurred to me about the ROB's on ARM cores being as big or bigger than on x86 these days. Since AFAIK the ARM cores do not support SMT and the ROB is split between threads when SMT is active, the ARM cores arguably have even more OoO HW relative to x86 on a per-thread basis.

OK rephrase then. What is it called when you execute a main and a dependency on the same circle? I cannot tell because i cannot find other hardware like that. Basically an ASIC for a few algorithms.

[bridgman]

OK rephrase then. What is it called when you execute a main and a dependency on the same circle? I cannot tell because i cannot find other hardware like that. Basically an ASIC for a few algorithms.

Can you use a few different words ? I don't think I'm understanding your question yet.

The closest thing I can think of is a couple of threads executing on the same core (SMT) and sharing execution resources dynamically.

[artivision]

Can you use a few different words ? I don't think I'm understanding your question yet.

The closest thing I can think of is a couple of threads executing on the same core (SMT) and sharing execution resources dynamically.

Explanation the best i can in english: You have one single thread with 5 main independent equations to solve. Those have parts (A) inside that you mast know / solve first in order to solve the main thing (B). Out of order processors solve all the 5 (A) parts on the first circle and all the 5 (B) on the second. X86 solves both some (A) and some (B) in one circle on many algorithms. Its OoO in time VS OoO in space with a crazy amount of space in use.

[Tomin]

I think artivision might be talking about speculative execution.

[bridgman]

Explanation the best i can in english: You have one single thread with 5 main independent equations to solve. Those have parts (A) inside that you mast know / solve first in order to solve the main thing (B). Out of order processors solve all the 5 (A) parts on the first circle and all the 5 (B) on the second. X86 solves both some (A) and some (B) in one circle on many algorithms. Its OoO in time VS OoO in space with a crazy amount of space in use.

I think artivision might be talking about speculative execution.

It's possible, but they may also be talking about the fact that OOO processors (whether X86 or some other ISA) don't know or care if the developer thought about separate sections of code as being logically independent - they just look as far ahead as their instruction window allows. This is done partially to identify any bits of code that can be executed independently, but arguably even more importantly to get memory accesses started early so that the results can be ready before the core stalls waiting for results.

artivision , one thing I don't understand is why you distinguish between "out of order processors" and "x86" since they all use the same OOO logic.

[tuxd3v]

No. You can compile the same application for both and measure its performance. It won't matter one bit what the binary code or underlying uArch is.

Its not that simple..
There are ways to cheat, on the benchmarks