Alibaba Crafts A 16-Core RISC-V Chip @ 2.5GHz

[George99]

Something which seems strange to me is that there are instructions to do XLEN*XLEN=2*XLEN multiplications but no way to devide 2*XLEN/XLEN=XLEN for either XLEN=32 bits or 64 bits architectures...?

[programmerjake]

Something which seems strange to me is that there are instructions to do XLEN*XLEN=2*XLEN multiplications but no way to devide 2*XLEN/XLEN=XLEN for either XLEN=32 bits or 64 bits architectures...?

the reason for that I would assume is that a 2*XLEN by XLEN division requires 3 integer source registers. risc-v's base instruction sets go out of their way to only need integer instructions to have 2 source registers and one destination register (notice the lack of load or store instructions that add two registers to form the address, the store would require 3 source regs), since that makes the HW much simpler for small implementations. XLEN * XLEN -> 2*XLEN multiplication only requires 2 source registers and one dest register, since it is split into two separate instructions, they produce the high and low halves of the product.

[rabcor]

Hype! give risc-v PC plz.

[dungeon]

IMO, for any half-decent out-of-order CPU, 10x is way too high... unless CoreMark can seriously utilize stuff like AVX.

Should we be dividing by the core count? That would yield 9.65 Coremark/MHz, if we treat it as 8-core. If 16-core, then half that... but obviously those aren't 16 full cores.

CoreMark/MHz seems means score just divided by MHz of a single core ... look at their scores list, x86 usually scores much more than else:

https://www.eembc.org/coremark/scores.php

If we calculate it like this, then this Raspberry Pi 4 would score 13 CM/Mhz there:

https://openbenchmarking.org/result/...AS-RASPBERRY18

[George99]

the reason for that I would assume is that a 2*XLEN by XLEN division requires 3 integer source registers. risc-v's base instruction sets go out of their way to only need integer instructions to have 2 source registers and one destination register (notice the lack of load or store instructions that add two registers to form the address, the store would require 3 source regs), since that makes the HW much simpler for small implementations. XLEN * XLEN -> 2*XLEN multiplication only requires 2 source registers and one dest register, since it is split into two separate instructions, they produce the high and low halves of the product.

While this sounds reasonable for me it could have been done the same way they did with MULH, a "DIVH" instruction to load the upper XLEN bits of the dividend followed by a DIV to do the math for the 2*XLEN / XLEN case. A little more complex than the MULH/MUL pair, of course.

[brad0]

The fact that this design is proprietary is a perfect example of why permissive licenses are bad. If RISC-V was copylefted, people would be going through the publicly available design right now, and could consider grouping together to order these chips from a fab.

I feel bad for how wrong you are. Get a clue.

[ldesnogu]

My i7-8650U gets 8 CoreMark / MHz.

CoreMark is a very poor benchmark: as previously wrote it doesn't stress anything but L1 cache; there's no branch mispredict; and it's very sensitive to peculiar optimizations (see this for instance).

It's not much better than Dhrystone. And is certainly not very significant for AI-or 5G like workloads

Anyway the RISC-V result looks interesting. But I will wait for results on more involved benchmarks

[starshipeleven]

The fact that this design is proprietary is a perfect example of why permissive licenses are bad. If RISC-V was copylefted, people would be going through the publicly available design right now, and could consider grouping together to order these chips from a fab.

That's a helluva "grouping together" you are looking at, to keep costs anywhere near something a consumer could actually afford you need to order millions of units.

[Guest]

That's a helluva "grouping together" you are looking at, to keep costs anywhere near something a consumer could actually afford you need to order millions of units.

It's still possible. It's not really about how many people will need these chips, but that it's possible to do.

[Guest]

I don't think it works like that. RISC-V is just the ISA - the functional description of the architecture. An implementation thereof wouldn't necessarily inherit the license, in a similar way (although not exactly analogous) to how code compiled with a GPL compiler doesn't become GPL'd.

And if the ISA were licensed in some way that forced all implementations to be open source, I doubt it would have the kind of traction that it's been getting. I don't care to argue this point - it's just my opinion.

ISA isn't like a compiler. A better analogy would be a proprietary compiler for a language with a free license.